专利内容由知识产权出版社提供
专利名称：WAFER LEVEL PACKAGE AND METHOD OF
FABRICATING THE SAME
发明人：Hyun-Soo CHUNG,In-Young LEE,Son-Kwan
HWANG,Dong-Ho LEE,Seong-Deok HWANG
申请号：US124913申请日：20090707
公开号：US20090267211A1公开日：20091029
专利附图：
摘要：Wafer level packages and methods of fabricating the same are provided. In oneembodiment, one of the methods comprises forming semiconductor chips having a
connection pad on a wafer, patterning a bottom surface of the wafer to form a trenchunder the connection pad, patterning a bottom surface of the trench to form a via holeexposing the bottom surface of the connection pad, and forming a connecting deviceconnected to the connection pad through the via hole. The invention provides a waferlevel package having reduced thickness, lower fabrication costs, and increased reliabilitycompared to conventional packages.
申请人：Hyun-Soo CHUNG,In-Young LEE,Son-Kwan HWANG,Dong-Ho LEE,Seong-DeokHWANG
地址：Gyeonggi-do KR,Gyeonggi-do KR,Gyeonggi-do KR,Gyeonggi-do KR,Seoul KR
国籍：KR,KR,KR,KR,KR
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