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专利名称：WAFER LEVEL PACKAGE AND FABRICATION
METHOD THEREOF
发明人：Shing-Yih Shih,Neng-Tai Shih,Hsu Chiang申请号：US14745473申请日：20150622
公开号：US20160372395A1公开日：20161222
专利附图：
摘要：A semiconductor device includes a semiconductor device includes an interposerhaving a first side and a second side opposite to the first side, wherein the interposercomprises a redistribution layer (RDL), and the RDL comprises a first passivation layer on
the first side and a second passivation layer on the second side; at least one active chipmounted on the first passivation layer on the first side through a plurality of first bumpspenetrating through the first passivation layer; a molding compound disposed on thefirst side, the molding compound covering the at least one active chip and a top surfaceof the first passivation layer; and a plurality of solder bumps mounted on the firstpassivation layer on the second side.
申请人：INOTERA MEMORIES, INC.
地址：Taoyuan City TW
国籍：TW
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