TPC10 S在RIES
CMOS FIELD-PROGRAMMABL在GATEARRAYS
$院FS001F -D38号。ξCEMBEF奇19RE飞／ISEDFEBRUARY 1993
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Four Arrays With叩to2000 UsableEquivalent Gates
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TPC10 Series FPGA Die Archite窑ture
丁heTexas Instruments (Tl）τPC10 Series comprises four field-programmable gate arrays (FPGAs）.τheTPC1010A, TPC1010日，TPC1020A,and TPC1020B FPGAs are fabricated using theτi silicon-gateCMOS process.τhe process features polysilicon gate, source, drain elements, and two levels ofcopper楠doped-aluminummetallization to reduce internal resistance and enhance performance. Typical diearchitecture is illustrated above.
τhese fieldprogrammabledevices combine gate-array flexibility with desktop programmability. This combination allows the designer to avoid fabrication cycle times and nonrecurring engineering charges associated with conventional maskprogramm硝gatearrays.τhe FPGAs are unique in that the arrays are fabricated, tested警andshipped to the user for programming. The俨PGAcontains user心onfigurableinputs, outputs, logic modules, and minimum-skew clock driver with hardwired distribution network. The FPGA also includes on-chip diagnostic probe capabilities and security fuses to protect the proprietary design.
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τable 1. Product Family Profile
DEVICE Capacity Gate a时ayequivalent gates τTL equivalent packag出CMOS Process LogicModul台$
Flip-Flops {maximum) Antiluses rizont母ITracks Vertie击iTracks τPC1010A 1200 34 1.2µm 295 130 112,000 22 13 τPC1极OA2000 53 1.2抖m273 18毡，00022 13 TPC101号B1200
34
τPC1020B 2000
53
”。1.0µm 295 130 112,000 22 13 1,1)µ硝… 气棋273186,000 22 13 川＇
TPC10 SERIES
CMOS FIELD-PROGRAMMABLE GATE ARRAYS
SRFS001 F -038, DECEMBER 19 -REVISED FEBRUARY 1993
electrical characteristics over full ranges of recommended peratingconditions (unless otherwise nted)
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PARAMETER
High level output voltage V OH (see Note 3)
Low level output voltage V OL (see Note 3) t nput current
oz Off-state output current
TEST CONDITIONS QH=-4mA QH =-3.2 mA QL =4mA
CSUFFIX
MIN TYPt MAX 3.84
0.33
I SUFFIX
MIN TYPt MAX 3.7
M SUFFIX
UNπ
MIN TYPt MAX 3.7
0.4
V V
。.4
±10 µA ±10 ±10 V1=Vccoro
士10±10 ±10 Vo= Vee orO µA 140 140 20 20 140 20 Vo=Vee Short-circuit output mA 10s
current (see Note 4) -100 -10-100-10 100 -10 Vo=O
supply V1 = Vee oro, 20 3 25 mA 10 3 3 tee Standby Outputs open current
7 eio Input/output capacitance Vo=O, 7 pf 7
I= 1 MHz (see N。te5)
t Typical values are at Vee = 5 V, TA = 25。e.
NOTES: 3. These limits apply when all other outputs are open.
4.When testing TPe 1 01 OA and TPe1020A, not more than one output sh。uldbe shorted at a time, and duration of the short circuit sh。uld
e1020Bnot exceed one second. The los parameter does not apply to TPe101 OBor TP
5.These limits apply for each user /0 pinswitching characteristics
The following tables summarize switching characteristics of various classes of TPC 1 O Series logic『nodulehardwired macros. An unloaded logic module propagation delay time is 4 ns. All other delays shown include the module delay time and statistical estimates for wiring delays based on 85% to 95% FPGA logic module utilizatio『1.Module utilization above 95% can result in performance degradation. Actual delay values are determined after place and route is accomplished using the ALS. ALS provides for assigning criticality to nets, automatic balancing of clock buffer loads, and utilizing long horizontal or vertical nets fo『connectingnoncritical functions. For specific timing parameters pe同ainingto a hardwired logic module, refer to the individual mac「Olibrary specification.
The ALS provides a capability to assign one of four levels of criticality to logic module output nets. The switching characteristics reflect the delay time differences for nets with criticality and without criticality assigned. Nets assigned as critical will be limited to a fan-out of 6 loads by the ALS. Clock load balancing, selectable by the designer, can be specified as moderate, strong, or ve「yst『ongto control clock skew.
