IS66WV51216BLL-55TLI;IS66WV51216BLL-55TLI-TR;中文规格书,Datasheet资料

ULTRA LOW POWER PSEUDO CMOS STATIC RAM

JANUARY 2010

FEATURES

•󰀀

•󰀀 󰀀•󰀀󰀀󰀀•󰀀•󰀀•󰀀•󰀀

High-speed󰀀access󰀀time:󰀀󰀀55nsCMOS󰀀low󰀀power󰀀operation– mW (typical) operating

–󰀀󰀀µW󰀀(typical)󰀀CMOS󰀀standbySingle󰀀power󰀀supply󰀀󰀀

–󰀀1.7V--1.95V󰀀Vdd (66WV51216ALL) (70ns)–󰀀2.5V--3.6V󰀀Vdd (66WV51216BLL) (55ns)Three󰀀state󰀀outputs

Data󰀀control󰀀for󰀀upper󰀀and󰀀lower󰀀bytesIndustrial󰀀temperature󰀀available󰀀Lead-free󰀀available󰀀

bit󰀀static󰀀RAMs󰀀organized󰀀as󰀀512K󰀀words󰀀by󰀀16󰀀bits.󰀀It󰀀is󰀀fabricated using ISSI's󰀀high-performance󰀀CMOS󰀀technology.󰀀This󰀀highly󰀀reliable󰀀process󰀀coupled󰀀with󰀀innovative󰀀circuit󰀀design󰀀techniques,󰀀yields󰀀high-performance󰀀and󰀀low󰀀power󰀀consumption devices.

When CS1󰀀is󰀀HIGH󰀀(deselected)󰀀or󰀀when󰀀CS2󰀀is󰀀LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB󰀀are󰀀HIGH,󰀀the󰀀device󰀀assumes󰀀a󰀀standby󰀀mode󰀀at which the power dissipation can be reduced down with CMOS󰀀input󰀀levels.

Easy memory expansion is provided by using Chip Enable and󰀀Output󰀀Enable󰀀inputs.󰀀The󰀀active󰀀LOW󰀀Write󰀀Enable󰀀(WE) controls both writing and reading of the memory. A data󰀀byte󰀀allows󰀀Upper󰀀Byte󰀀(UB)󰀀and󰀀Lower󰀀Byte󰀀(LB) access.

The󰀀IS66WV51216ALL/BLL󰀀is󰀀packaged󰀀in󰀀the󰀀JEDEC󰀀standard󰀀48-pin󰀀mini󰀀BGA󰀀(6mm󰀀x󰀀8mm)󰀀and󰀀44-Pin󰀀TSOP󰀀(TYPE󰀀II).󰀀The󰀀device󰀀is󰀀aslo󰀀available󰀀for󰀀die󰀀sales.

DESCRIPTION

The󰀀ISSI󰀀IS66WV51216ALL/BLL󰀀is󰀀a󰀀high-speed,󰀀8M󰀀

FUNCTIONAL BLOCK DIAGRAM

A0-A18DECODER512K x 16MEMORY ARRAYVDDGNDI/O0-I/O7Lower ByteI/O8-I/O15Upper ByteI/ODATACIRCUITCOLUMN I/OCS2CS1OEWEUBLBCONTROLCIRCUITCopyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

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Rev. A12/02/09

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IS66WV51216ALLIS66WV51216BLLPIN CONFIGURATIONS: 512K x 18-Pin mini BGA (6mm x 8mm)

1 2 3 4 5 6A4A3A2A1A0CS1I/O0I/O1I/O2I/O3VDDGNDI/O4I/O5I/O6I/O7WEA16A15A14A13A1212345671011121314151617181920212244434241403938373635343332313029282726252423A5A6A7OEUBLBI/O15I/O14I/O13I/O12GNDVDDI/O11I/O10I/O9I/O8A18A8A9A10A11A1744-Pin TSOP (Type II)

ABCDEFGHLBI/O8I/O9GNDVDDI/O14I/O15A18OEUBI/O10I/O11I/O12I/O13NCA8A0A3A5A17NCA14A12A9A1A4A6A7A16A15A13A10A2CS1I/O1I/O3I/O4I/O5WEA11CS2I/O0I/O2VDD`GNDI/O6I/O7NCPIN DESCRIPTIONS

A0-A18󰀀Address󰀀InputsI/O0-I/O15󰀀Data󰀀Inputs/OutputsCS1, CS2 Chip Enable InputOE󰀀󰀀Output󰀀Enable󰀀InputWE Write Enable InputLB󰀀Lower-byte󰀀Control󰀀(I/O0-I/O7)UB󰀀Upper-byte󰀀Control󰀀(I/O8-I/O15)NC No ConnectionPowerVdd󰀀GND󰀀Ground2

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IS66WV51216ALLIS66WV51216BLLTRUTH TABLE

󰀀󰀀

󰀀󰀀󰀀 󰀀󰀀

Mode

Not󰀀Selected󰀀󰀀󰀀

Output󰀀Disabled󰀀󰀀

Read󰀀󰀀

Write󰀀󰀀 WE X󰀀X󰀀X󰀀H󰀀H󰀀H󰀀H󰀀H L󰀀L󰀀L CS1 CS2 OE H󰀀X󰀀X󰀀X󰀀L󰀀X󰀀X󰀀X󰀀X󰀀L󰀀H󰀀H󰀀L󰀀H󰀀H󰀀L󰀀H󰀀L󰀀L󰀀H󰀀L󰀀L H L L󰀀H󰀀X󰀀L󰀀H󰀀X󰀀L H X

LB X󰀀X󰀀H󰀀L󰀀X󰀀L󰀀H󰀀L L󰀀H󰀀L UB X󰀀X󰀀H󰀀X󰀀L󰀀H󰀀L󰀀L H󰀀L󰀀L I/O PIN

I/O0-I/O7 I/O8-I/O15 High-Z󰀀High-Z󰀀High-Z󰀀High-Z󰀀High-Z󰀀High-Z󰀀High-Z󰀀High-Z󰀀High-Z󰀀High-Z󰀀dout󰀀High-Z High-Z󰀀dout dout doutdIn󰀀High-Z High-Z󰀀dIn dIn dIn

Vdd Current

IsB1, IsB2 IsB1, IsB2 IsB1, IsB2

Icc IccIcc Icc OPERATING RANGE (Vdd)

Range

Ambient Temperature

(70ns)

(55ns)

(70ns)

Commercial󰀀

Industrial󰀀󰀀Automotive󰀀

0°C󰀀to󰀀+70°C󰀀–40°C󰀀to󰀀+85°C󰀀–40°C󰀀to󰀀+105°C󰀀

1.7V󰀀-󰀀1.95V󰀀1.7V󰀀-󰀀1.95V󰀀

󰀀

2.5V󰀀-󰀀3.6V󰀀󰀀2.5V󰀀-󰀀3.6V

󰀀

2.5V-3.6V󰀀

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IS66WV51216ALLIS66WV51216BLLABSOLUTE MAXIMUM RATINGS(1)

Symbol Vterm tBIAs Vdd tstg Pt

Parameter

Terminal󰀀Voltage󰀀with󰀀Respect󰀀to󰀀GND󰀀Temperature󰀀Under󰀀Bias󰀀Vdd Related󰀀to󰀀GND󰀀Storage󰀀Temperature󰀀Power󰀀Dissipation󰀀

Value

–0.2󰀀to󰀀Vdd+0.3󰀀–40󰀀to󰀀+85󰀀–0.2󰀀to󰀀+3.8󰀀–65󰀀to󰀀+150󰀀

1.0󰀀

UnitV°CV°CW

Note:1.󰀀󰀀Stress󰀀greater󰀀than󰀀those󰀀listed󰀀under󰀀ABSOLUTE󰀀MAXIMUM󰀀RATINGS󰀀may󰀀cause󰀀permanent󰀀damage󰀀to󰀀the󰀀device.󰀀This󰀀is󰀀a󰀀stress󰀀rating󰀀only󰀀and󰀀functional󰀀operation󰀀of󰀀the󰀀device󰀀at󰀀these󰀀or󰀀any󰀀other󰀀conditions󰀀above󰀀those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rat-ing conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS (Over󰀀Operating󰀀Range)

󰀀 Symbol VoH VoL VIH VIL(1) 󰀀ILI ILo Parameter

Output󰀀HIGH󰀀Voltage󰀀

Output󰀀LOW󰀀Voltage󰀀

Input󰀀HIGH󰀀Voltage󰀀

Input󰀀LOW󰀀Voltage 󰀀

Input󰀀Leakage󰀀Output󰀀Leakage Test Conditions Vdd IoH = -0.1󰀀mA󰀀1.7-1.95V󰀀IoH = -1󰀀mA󰀀2.5-3.6V󰀀IoL = 0.1󰀀mA󰀀1.7-1.95V󰀀IoL = 2.1󰀀mA󰀀2.5-3.6V󰀀󰀀1.7-1.95V󰀀 2.5-3.6V󰀀󰀀1.7-1.95V󰀀󰀀2.5-3.6V󰀀GND󰀀≤ VIn ≤ Vdd

GND󰀀≤ Vout ≤ Vdd, Outputs󰀀Disabled󰀀Min. 1.4󰀀2.2󰀀—󰀀—󰀀1.4󰀀2.2󰀀–0.2󰀀–0.2󰀀–1 –1󰀀Max. —󰀀—󰀀0.2󰀀0.4󰀀Vdd + 0.2 Vdd + 0.3 0.4󰀀0.6󰀀1 1󰀀UnitV󰀀VV󰀀VV VV󰀀VµAµANotes:1. VIL (min.) = –1.0V for pulse width less than 10 ns.

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IS66WV51216ALLIS66WV51216BLLCAPACITANCE(1)

Symbol cIn cout󰀀Parameter

Input Capacitance Input/Output󰀀Capacitance󰀀Conditions VIn = 0V Vout = 0V Max. 8 10 UnitpFpFNote:1.󰀀󰀀Tested󰀀initially󰀀and󰀀after󰀀any󰀀design󰀀or󰀀process󰀀changes󰀀that󰀀may󰀀affect󰀀these󰀀parameters.

AC TEST CONDITIONS

󰀀󰀀󰀀󰀀

Parameter

Input󰀀Pulse󰀀Level󰀀

Input󰀀Rise󰀀and󰀀Fall󰀀Times󰀀Input󰀀and󰀀Output󰀀Timing󰀀and󰀀Reference󰀀LevelOutput󰀀Load󰀀

1.7V-1.95V (Unit)

0.4V󰀀to󰀀Vdd-0.2󰀀

5󰀀ns󰀀Vref See󰀀Figures󰀀1󰀀and󰀀2󰀀

2.5V-3.6V (Unit)

0.4V󰀀to󰀀Vdd-0.3V

5ns

Vref

See󰀀Figures󰀀1󰀀and󰀀2

󰀃

r1(Ω) R2(Ω)󰀃Vref Vtm󰀀1.7V - 1.95V

3070󰀀3150󰀀0.9V 1.8V󰀀2.5V - 3.6V102917281.4V2.8VAC TEST LOADS

R1VTMOUTPUT30 pFIncludingjig andscopeR2VTMOUTPUT5 pFIncludingjig andscopeR2R1Figure 1Figure 2Integrated Silicon Solution, Inc. — www.issi.com 󰀀

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IS66WV51216ALLIS66WV51216BLL1.7V-1.95V POWER SUPPLY CHARACTERISTICS(1) (Over󰀀Operating󰀀Range)

Symbol Icc 󰀀󰀀 Icc1 IsB1 󰀀󰀀 󰀀 󰀀 󰀀 IsB2󰀀󰀀 Parameter Vdd󰀀Dynamic󰀀Operating󰀀Supply Current 󰀀 Operating󰀀Supply󰀀Current TTL󰀀Standby󰀀Current󰀀(TTL󰀀Inputs)󰀀 OR

ULB󰀀Control󰀀

CMOS󰀀Standby󰀀Current󰀀(CMOS󰀀Inputs)󰀀 OR

ULB󰀀Control󰀀 Vdd󰀀=󰀀Max.,󰀀CS1 = VIL, cs2=VIH

VIn ≥ Vdd – 0.2V, or VIn ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Vdd󰀀=󰀀Max.,󰀀VIn = VIH or VILCS1 = VIL, f = 0, UB = VIH, LB = VIHVdd = Max.,󰀀 Com. CS1 ≥ Vdd – 0.2V, Ind. CS2 ≤󰀀󰀀0.2V,󰀀Auto.󰀀VIn ≥ Vdd – 0.2V, or typ.(1) VIn ≤ 0.2V, f = 0Test Conditions Vdd = Max.,󰀀Iout = 0 mA, f = fmAX All󰀀Inputs󰀀󰀀0.4V󰀀󰀀󰀀or Vdd – 0.2V Vdd = Max., CS1 = 0.2V WE = Vdd – 0.2V CS2 = Vdd – 0.2V, f = 1mHz Vdd = Max., VIn = VIH or VIL CS1 = VIH , CS2 = VIL, f󰀀=󰀀1󰀀MHz Com.󰀀Ind.󰀀Auto.󰀀typ.(1)Com. Ind. Auto. Com. Ind. Auto. 󰀀󰀀󰀀 󰀀󰀀󰀀 Max. 70ns20󰀀25󰀀30󰀀4 410 0.6 0.6 1 UnitmA 󰀀󰀀󰀀󰀀mA 󰀀󰀀󰀀󰀀mA 󰀀 󰀀 100 120 150 µA 󰀀󰀀 Note:.1.󰀀󰀀Typical󰀀values󰀀are󰀀measured󰀀at󰀀Vdd󰀀=󰀀1.8V,󰀀TA󰀀=󰀀25oC and not 100% tested.

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IS66WV51216ALLIS66WV51216BLL2.5V-3.6V POWER SUPPLY CHARACTERISTICS(1) (Over󰀀Operating󰀀Range)

Symbol Icc Icc1 IsB1 󰀀󰀀 󰀀 󰀀 󰀀 IsB2󰀀󰀀 Parameter Vdd Dynamic󰀀Operating󰀀Supply Current Operating󰀀Supply󰀀Current TTL󰀀Standby󰀀Current󰀀(TTL󰀀Inputs)󰀀 OR

ULB󰀀Control󰀀

CMOS󰀀Standby󰀀Current󰀀(CMOS󰀀Inputs)󰀀 OR

ULB󰀀Control󰀀 Vdd󰀀=󰀀Max.,󰀀CS1 = VIL, cs2=VIH

VIn ≥ Vdd – 0.2V, or VIn ≤ 0.2V, f = 0; UB / LB = Vdd – 0.2V Vdd󰀀=󰀀Max.,󰀀VIn = VIH or VILCS1 = VIL, f = 0, UB = VIH, LB = VIHVdd = Max.,󰀀 Com. CS1 ≥ Vdd – 0.2V, Ind. CS2 ≤󰀀󰀀0.2V,󰀀Auto.󰀀VIn ≥ Vdd – 0.2V, or typ.(2)󰀀VIn ≤ 0.2V, f = 0 Test Conditions Vdd = Max.,󰀀Com.󰀀Iout = 0 mA, f = fmAX Ind.󰀀All Inputs 0.4V󰀀Auto.󰀀or Vdd –󰀀0.3V󰀀typ.(2)󰀀Vdd = Max., CS1 = 0.2V󰀀Com.󰀀WE = Vdd – 0.2V Ind.󰀀CS2 = Vdd – 0.2V, f = 1mHz Auto. Vdd = Max., Com. VIn = VIH or VIL Ind. CS1 = VIH , CS2 = VIL, Auto. f󰀀=󰀀1󰀀MHz 󰀀󰀀󰀀󰀀󰀀󰀀 󰀀󰀀󰀀󰀀󰀀󰀀 Max. 55ns 25󰀀28󰀀35󰀀155󰀀5󰀀100.6 0.6 1 󰀀󰀀󰀀󰀀󰀀 UnitmA 󰀀󰀀mA 󰀀󰀀󰀀󰀀mA 󰀀󰀀 󰀀󰀀100 130 150󰀀75 󰀀µA 󰀀󰀀 Note:1. At f = fmAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.2.󰀀󰀀Typical󰀀values󰀀are󰀀measured󰀀at󰀀Vdd󰀀=󰀀3.0V,󰀀TA󰀀=󰀀25oC and not 100% tested.

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IS66WV51216ALLIS66WV51216BLLREAD CYCLE SWITCHING CHARACTERISTICS(1) (Over󰀀Operating󰀀Range)

Symbol trc󰀀 tAA󰀀 toHA󰀀

tAcs1/tAcs2 tdoe tHzoe(2) tLzoe(2)

tHzcs1/tHzcs2(2) tLzcs1/tLzcs2(2) tBA tHzB tLzB

55 ns 70 ns

Parameter Min. Max. Min. Max. Read󰀀Cycle󰀀Time󰀀󰀀󰀀55󰀀—󰀀70󰀀—󰀀Address󰀀Access󰀀Time󰀀󰀀󰀀—󰀀55󰀀—󰀀70󰀀Output󰀀Hold󰀀Time󰀀󰀀󰀀10󰀀—󰀀10󰀀—󰀀CS1/CS2󰀀Access󰀀Time󰀀󰀀󰀀—󰀀55󰀀—󰀀70󰀀OE󰀀Access󰀀Time󰀀󰀀󰀀—󰀀25󰀀—󰀀35󰀀OE󰀀to󰀀High-Z󰀀Output󰀀󰀀󰀀—󰀀20󰀀—󰀀25󰀀OE󰀀to󰀀Low-Z󰀀Output󰀀󰀀󰀀5󰀀—󰀀5󰀀—󰀀CS1/CS2󰀀to󰀀High-Z󰀀Output󰀀󰀀󰀀0󰀀20󰀀0󰀀25󰀀CS1/CS2󰀀to󰀀Low-Z󰀀Output󰀀󰀀󰀀10󰀀—󰀀10󰀀—󰀀LB, UB󰀀Access󰀀Time󰀀󰀀󰀀—󰀀55󰀀—󰀀70󰀀LB, UB󰀀to󰀀High-Z󰀀Output󰀀LB, UB󰀀to󰀀Low-Z󰀀Output󰀀

󰀀󰀀

󰀀󰀀

0󰀀0󰀀

20󰀀—󰀀

0󰀀0󰀀

25󰀀—󰀀

Unitnsnsnsnsnsnsnsnsnsnsnsns

Notes: 1.󰀀Test󰀀conditions󰀀assume󰀀signal󰀀transition󰀀times󰀀of󰀀5󰀀ns󰀀or󰀀less,󰀀timing󰀀reference󰀀levels󰀀of󰀀0.9V/1.5V,󰀀input󰀀pulse󰀀levels󰀀of󰀀0.4󰀀to󰀀Vdd-0.2V/0.4V󰀀to󰀀Vdd-0.3V󰀀and󰀀output󰀀loading󰀀specified󰀀in󰀀Figure󰀀1.

2.󰀀Tested󰀀with󰀀the󰀀load󰀀in󰀀Figure󰀀2.󰀀Transition󰀀is󰀀measured󰀀±100󰀀mV󰀀from󰀀steady-state󰀀voltage.󰀀Not󰀀100%󰀀tested.

AC WAVEFORMS

READ CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = VIL, cs2 = WE = VIH, UB or LB = VIL)

tRCADDRESStAAtOHAtOHADATA VALIDDQ0-D15PREVIOUS DATA VALID8󰀀

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IS66WV51216ALLIS66WV51216BLLAC WAVEFORMS

READ CYCLE NO. 2(1,3) (CS1, CS2, OE,󰀀AND󰀀UB/LB Controlled)

tRCADDRESStAAtOHAOEtDOEtHZOECS1tACE1/tACE2tLZOECS2tLZCE1/tLZCE2tHZCS1/ tHZCS1LB, UBtLZBtBAtHZBDOUTHIGH-ZDATA VALIDNotes: 1. WE󰀀is󰀀HIGH󰀀for󰀀a󰀀Read󰀀Cycle.

2.󰀀The󰀀device󰀀is󰀀continuously󰀀selected.󰀀OE, CS1, UB, or LB = VIL. cs2=WE=VIH.3.󰀀Address󰀀is󰀀valid󰀀prior󰀀to󰀀or󰀀coincident󰀀with󰀀CS1󰀀LOW󰀀transition.

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IS66WV51216ALLIS66WV51216BLLWRITE CYCLE SWITCHING CHARACTERISTICS(1,2)󰀀(Over󰀀Operating󰀀Range)

Symbol tWc󰀀 tAW󰀀 tHA󰀀 tsA󰀀 tPWB tPWe(4) tsd󰀀 tHd󰀀 tHzWe(3) tLzWe(3)

Notes:

1.󰀀Test󰀀conditions󰀀assume󰀀signal󰀀transition󰀀times󰀀of󰀀5󰀀ns󰀀or󰀀less,󰀀timing󰀀reference󰀀levels󰀀of󰀀0.9V/1.5V,󰀀input󰀀pulse󰀀levels󰀀of󰀀󰀀0.4󰀀to󰀀Vdd-0.2V/0.4V󰀀to󰀀Vdd-0.3V󰀀and󰀀output󰀀loading󰀀specified󰀀in󰀀Figure󰀀1.

2. The󰀀internal󰀀write󰀀time󰀀is󰀀defined󰀀by󰀀the󰀀overlap󰀀of CS1 LOW,󰀀CS2󰀀HIGH󰀀and󰀀UB or LB, and WE󰀀LOW.󰀀All󰀀signals󰀀must󰀀be󰀀in󰀀valid󰀀states󰀀to󰀀initiate󰀀a󰀀Write,󰀀but󰀀any one can go inactive to terminate󰀀the󰀀Write.󰀀The󰀀Data󰀀Input󰀀Setup󰀀and󰀀Hold󰀀timing󰀀are󰀀referenced󰀀to󰀀the󰀀rising󰀀or󰀀falling󰀀edge󰀀of󰀀the󰀀signal󰀀that󰀀terminates󰀀the󰀀write.3.󰀀Tested󰀀with󰀀the󰀀load󰀀in󰀀Figure󰀀2.󰀀Transition󰀀is󰀀measured󰀀±100󰀀mV󰀀from󰀀steady-state󰀀voltage.󰀀Not󰀀100%󰀀tested.4. tPWe > tHzWe + tsd when OE󰀀is󰀀LOW.

Parameter Write󰀀Cycle󰀀Time󰀀

55 ns 70 ns Min. Max. Min. Max. 󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀󰀀

55󰀀45󰀀45󰀀0󰀀0󰀀45󰀀45󰀀25󰀀0󰀀—󰀀5󰀀

—󰀀—󰀀—󰀀—󰀀—󰀀—󰀀—󰀀—󰀀—󰀀20󰀀—󰀀

󰀀󰀀󰀀70󰀀󰀀󰀀󰀀60󰀀󰀀󰀀󰀀60󰀀󰀀󰀀󰀀󰀀󰀀0󰀀󰀀󰀀󰀀󰀀󰀀0󰀀󰀀󰀀󰀀60󰀀󰀀󰀀󰀀󰀀60󰀀󰀀󰀀󰀀30󰀀󰀀󰀀󰀀󰀀󰀀0󰀀󰀀󰀀󰀀󰀀󰀀—󰀀󰀀󰀀󰀀󰀀󰀀5󰀀

—󰀀—󰀀—󰀀—󰀀—󰀀—󰀀—󰀀—󰀀—󰀀30󰀀—󰀀

Unitnsnsnsnsnsnsnsnsns󰀀nsns

tscs1/tscs2 CS1/CS2󰀀to󰀀Write󰀀End󰀀

Address󰀀Hold󰀀from󰀀Write󰀀End󰀀Address󰀀Setup󰀀Time󰀀LB, UB󰀀Valid󰀀to󰀀End󰀀of󰀀Write󰀀WE󰀀Pulse󰀀Width󰀀Data󰀀Setup󰀀to󰀀Write󰀀End󰀀Data󰀀Hold󰀀from󰀀Write󰀀End󰀀WE󰀀LOW󰀀to󰀀High-Z󰀀Output󰀀WE󰀀HIGH󰀀to󰀀Low-Z󰀀Output󰀀

Address󰀀Setup󰀀Time󰀀to󰀀Write󰀀End󰀀󰀀󰀀󰀀󰀀󰀀

AC WAVEFORMS

WRITE CYCLE NO. 1(1,2) (CS1 Controlled, OE󰀀=󰀀HIGH󰀀or󰀀LOW)

tWCADDRESStSCS1tHACS1tSCS2CS2tAWtPWEWELB, UBtSAtHZWEtPWBtLZWEHIGH-ZDOUTDATA UNDEFINEDtSDtHDDINDATA-IN VALIDNotes: 1.󰀀WRITE󰀀is󰀀an󰀀internally󰀀generated󰀀signal󰀀asserted󰀀during󰀀an󰀀overlap󰀀of󰀀the󰀀LOW󰀀states󰀀on󰀀the󰀀CS1 , CS2 and WE inputs and at least one of the LB and UB󰀀inputs󰀀being󰀀in󰀀the󰀀LOW󰀀state.2.󰀀WRITE󰀀=󰀀(CS1) [ (LB) = (UB) ] (WE).

10

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Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

12/02/09

分销商库存信息:

ISSI

IS66WV51216BLL-55BLIIS66WV51216BLL-55TLI-TRIS66WV51216BLL-55BLI-IS66WV51216BLL-55TLITR