PCA9543BPW资料

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PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

Rev. 05 — 17 November 2008

Product data sheet

1.General description

The PCA9543A/43B/43C is a bidirectional translating switch, controlled by the I2C-bus.The SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any

individual SCx/SDx channels or combination of channels can be selected, determined bythe contents of the programmable control register. Two interrupt inputs,INT0 andINT1,oneforeachofthedownstreampairs,areprovided.Oneinterruptoutput,INT,whichactsas an AND of the two interrupt inputs, is provided.

AnactiveLOWresetinputallowsthePCA9543XtorecoverfromasituationwhereoneofthedownstreamI2C-busesisstuckinaLOWstate.PullingtheRESETpinLOWresetstheI2C-busstatemachineandcausesallthechannelstobedeselected,asdoestheinternalpower-on reset function.

ThepassgatesoftheswitchesareconstructedsuchthattheVDDpincanbeusedtolimitthemaximumhighvoltagewhichwillbepassedbythePCA9543X.Thisallowstheuseofdifferent bus voltages on each SCx/SDx pair, so that 1.8V, 2.5V, or 3.3V parts cancommunicate with 5V parts without any additional protection. External pull-up resistorspull the bus up to the desired voltage level for each channel. All I/O pins are 5V tolerant.The PCA9543A, PCA9543B and PCA9543C are identical except for the ﬁxed portion ofthe slave address.

2.Features

IIIIIIIIIIIIIII

1-of-2 bidirectional translating switches

I2C-bus interface logic; compatible with SMBus standards2 activeLOW interrupt inputsActiveLOW interrupt outputActiveLOW reset input

2 address pins allowing up to 4 devices on the I2C-bus

Alternate address versions A, B and C allow up to a total of 12 devices on the bus forlarger systems or to resolve address conﬂicts

Channel selection via I2C-bus, in any combinationPower-up with all switch channels deselectedLow Ron switches

Allows voltage level translation between 1.8V, 2.5V, 3.3V and 5V busesNo glitch on power-upSupports hot insertionLow standby current

Operating power supply voltage range of 2.3V to 5.5V

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

I5V tolerant inputs

I0Hz to 400kHz clock frequency

IESD protection exceeds 2000V HBM per JESD22-A114, 200V MM perJESD22-A115, and 1000V CDM per JESD22-C101

ILatch-up testing is done to JEDEC Standard JESD78 which exceeds 100mAIPackages offered: SO14, TSSOP14

3.Ordering information

Table 1.

Ordering information

PackageNamePCA9543ADPCA9543APWPCA9543BPWPCA9543CPW

SO14TSSOP14

Descriptionplastic small outline package; 14 leads;bodywidth3.9mm

plastic thin shrink small outline package; 14 leads;body width 4.4mm

VersionSOT108-1SOT402-1

Type number3.1Ordering options

Table 2.

Ordering options

Topside markPCA9543ADPA9543APA9543BPA9543C

Temperature range (Tamb)Tamb=−40°Cto+85°CTamb=−40°Cto+85°CTamb=−40°Cto+85°CTamb=−40°Cto+85°C

Type numberPCA9543ADPCA9543APWPCA9543BPWPCA9543CPW

Product data sheetRev. 05 — 17 November 20082 of 23

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

4.Block diagram

PCA9543A/43B/43CSC0SC1SD0SD1VSSVDDRESETSWITCH CONTROL LOGICPOWER-ONRESETSCLSDAINPUTFILTERI2C-BUSCONTROLA0A1INT0toINT1INTERRUPT LOGICINT002aab180Fig 1.Block diagram of PCA9543A/43B/43CPCA9543A_43B_43C_5© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 05 — 17 November 20083 of 23

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

5.Pinning information

5.1Pinning

A0A1RESETINT0SD0SC0VSS1234567002aab17814VDD13SDA12SCLA0A1RESETINT0SD0SC0VSS1234567002aab179PCA9543AD11INT10SC198SD1INT114VDD13SDAPCA9543APWPCA9543BPWPCA9543CPW12SCL11INT10SC198SD1INT1Fig 2.Pin conﬁguration for SO14Fig 3.Pin conﬁguration for TSSOP145.2Pin description

Table 3.SymbolA0A1RESETINT0SD0SC0VSSINT1SD1SC1INTSCLSDAVDD

Pin description

Pin12345671011121314

Descriptionaddress input 0address input 1activeLOW reset inputactiveLOW interrupt input 0serial data 0serial clock 0supply ground

activeLOW interrupt input 1serial data 1serial clock 1

activeLOW interrupt outputserial clock lineserial data linesupply voltage

Product data sheetRev. 05 — 17 November 20084 of 23

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

6.Functional description

Refer toFigure 1 “Block diagram of PCA9543A/43B/43C”.

6.1Device address

Following a START condition, the bus master must output the address of the slave it isaccessing. The address of the PCA9543A is shown inFigure4. To conserve power, nointernal pull-up resistors are incorporated on the hardware selectable address pins andthey must be pulled HIGH or LOW.

111fixed00A1A0R/Whardwareselectable002aab169Fig 4.Slave address PCA9543AThe last bit of the slave address deﬁnes the operation to be performed. When set tologic1 a read is selected, while a logic0 selects a write operation.

The PCA9543B and PCA9543C are alternate address versions if needed for larger

systemsortoresolveaddressconﬂicts.ThedatasheetwillreferencethePCA9543A,butthe PCA9543B and PCA9543C function identically except for the slave address.

111fixed10A1A0R/W011fixed00A1A0R/Whardwareselectable002aab799hardwareselectable002aab800Fig 5.Slave address PCA9543BFig 6.Slave address PCA9543C6.2Control register

Followingthesuccessfulacknowledgementoftheslaveaddress,thebusmasterwillsenda byte to the PCA9543A, which will be stored in the control register. If multiple bytes arereceivedbythePCA9543A,itwillsavethelastbytereceived.Thisregistercanbewrittenand read via the I2C-bus.

interrupt bits(read only)7X6X54INTINT103Xchannel selection bits(read/write)2X1B10B0channel 0channel 1INT0INT1002aab181Fig 7.PCA9543A_43B_43C_5

Product data sheetRev. 05 — 17 November 20085 of 23

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

6.2.1Control register deﬁnition

One or several SCx/SDx downstream pair, or channel, is selected by the contents of thecontrol register. This register is written after the PCA9543A has been addressed. The2LSBsofthecontrolbyteareusedtodeterminewhichchannelistobeselected.Whenachannel is selected, the channel will become active after a STOP condition has beenplaced on the I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state whenthe channel is made active, so that no false conditions are generated at the time ofconnection.

Table 4.D7XX0

D6XX0

Control register: Write—channel selection; Read—channel status

INT1XX0

INT0XX0

D3XX0

D2XX0

B1X010

B001X0

Commandchannel0 disabledchannel0 enabledchannel1 disabledchannel1 enabled

no channel selected;

power-up/reset default state

Remark:Channel0 and channel1 can be enabled at the same time. Care should betaken not to exceed the maximum bus capacitance.

6.2.2Interrupt handling

The PCA9543A provides 2 interrupt inputs, one for each channel, and one open-draininterrupt output. When an interrupt is generated by any device, it will be detected by thePCA9543A and the interrupt output will be driven LOW. The channel need not be activefor detection of the interrupt. A bit is also set in the control register.

Bit4 and bit5 of the control register corresponds to theINT0 andINT1 inputs of thePCA9543A, respectively. Therefore, if an interrupt is generated by any device connectedto channel1, the state of the interrupt inputs is loaded into the control register when areadisaccomplished.Likewise,aninterruptonanydeviceconnectedtochannel0wouldcause bit4 of the control register to be set on the read. The master can then address thePCA9543A and read the contents of the control register to determine which channelcontains the device generating the interrupt. The master can then reconﬁgure thePCA9543A to select this channel, and locate the device generating the interrupt andclearit.

Itshouldbenotedthatmorethanonedevicecanprovideaninterruptonachannel,soitisup to the master to ensure that all devices on a channel are interrogated for an interrupt.Theinterruptinputsmaybeusedasgeneralpurposeinputsiftheinterruptfunctionisnotrequired.

If unused, interrupt input(s) must be connected to VDD through a pull-up resistor.

Table 5.7XX

PCA9543A_43B_43C_5

Control register: Read—interrupt6XX

INT1X01

INT001X

3XX

2XX

B1XX

B0XX

Commandno interrupt on channel0interrupt on channel0no interrupt on channel1interrupt on channel1

Product data sheetRev. 05 — 17 November 20086 of 23

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

Remark:Two interrupts can be active at the same time.

6.3RESET inputTheRESET input is an activeLOW signal which may be used to recover from a bus faultcondition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9543A will resetits registers and I2C-bus state machine and will deselect all channels. TheRESET inputmust be connected to VDD through a pull-up resistor.

6.4Power-on reset

WhenpowerisappliedtoVDD,aninternalPower-OnReset(POR)holdsthePCA9543AinaresetconditionuntilVDDhasreachedVPOR.Atthispoint,theresetconditionisreleasedand the PCA9543A registers and I2C-bus state machine are initialized to their defaultstates (all zeroes) causing all the channels to be deselected. Thereafter, VDD must belowered below 0.2V to reset the device.

6.5Voltage translation

ThepassgatetransistorsofthePCA9543AareconstructedsuchthattheVDDvoltagecanbe used to limit the maximum voltage that will be passed from one I2C-bus to another.

5.0Vo(sw)(V)4.0(1)(2)(3)002aaa93.02.01.02.02.53.03.54.04.55.55.0VDD (V)(1)maximum(2)typical(3)minimumFig 8.Pass gate voltage versus supply voltageFigure8showsthevoltagecharacteristicsofthepassgatetransistors(notethatthegraphwas generated using the data speciﬁed inSection 10 “Static characteristics” of this datasheet).InorderforthePCA9543Atoactasavoltagetranslator,theVo(sw)voltageshouldbe equal to, or lower than the lowest bus voltage. For example, if the main bus wasrunning at 5V, and the downstream buses were 3.3V and 2.7V, then Vo(sw) should beequal to or below 2.7V to effectively clamp the downstream bus voltages. Looking at

Product data sheetRev. 05 — 17 November 20087 of 23

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PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

Figure8, we see that Vo(sw)(max) will be at 2.7V when the PCA9543A supply voltage is3.5V or lower, so the PCA9543A supply voltage could be set to 3.3V. Pull-up resistorscan then be used to bring the bus voltages to their appropriate levels (seeFigure15).MoreInformationcanbefoundinApplicationNoteAN262:PCA954XfamilyofI2C/SMBusmultiplexers and switches.

7.Characteristics of the I2C-bus

TheI2C-busisfor2-way,2-linecommunicationbetweendifferentICsormodules.Thetwolines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be

connected to a positive supply via a pull-up resistor when connected to the output stagesof a device. Data transfer may be initiated only when the bus is not busy.

7.1Bit transfer

Onedatabitistransferredduringeachclockpulse.ThedataontheSDAlinemustremainstable during the HIGH period of the clock pulse as changes in the data line at this timewill be interpreted as control signals (seeFigure9).

SDASCLdata linestable;data validchangeof dataallowedmba607Fig 9.Bit transfer7.2START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

transitionofthedatalinewhiletheclockisHIGHisdeﬁnedastheSTARTcondition(S).ALOW-to-HIGH transition of the data line while the clock is HIGH is deﬁned as the STOPcondition (P) (seeFigure10).

Product data sheetRev. 05 — 17 November 20088 of 23

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PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

7.3System conﬁguration

A device generating a message is a ‘transmitter’, a device receiving is the ‘receiver’. Thedevice that controls the message is the ‘master’ and the devices which are controlled bythe master are the ‘slaves’ (seeFigure11).

SDASCLMASTERTRANSMITTER/RECEIVERSLAVERECEIVERSLAVETRANSMITTER/RECEIVERMASTERTRANSMITTERMASTERTRANSMITTER/RECEIVERI2C-BUSMULTIPLEXERSLAVE002aaa966Fig 11.System conﬁguration7.4Acknowledge

The number of data bytes transferred between the START and the STOP conditions fromtransmitter to receiver is not limited. Each byte of eight bits is followed by one

acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter,whereas the master generates an extra acknowledge related clock pulse.

Aslavereceiverwhichisaddressedmustgenerateanacknowledgeafterthereceptionofeachbyte.Also,amastermustgenerateanacknowledgeafterthereceptionofeachbytethat has been clocked out of the slave transmitter. The device that acknowledges has topulldowntheSDAlineduringtheacknowledgeclockpulse,sothattheSDAlineisstableLOW during the HIGH period of the acknowledge related clock pulse; setup and holdtimes must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating anacknowledge on the last byte that has been clocked out of the slave. In this event, thetransmitter must leave the data line HIGH to enable the master to generate a STOPcondition.

data outputby transmitternot acknowledgedata outputby receiveracknowledgeSCL from masterSSTARTcondition128clock pulse foracknowledgement9002aaa987Fig 12.Acknowledgement on the I2C-busPCA9543A_43B_43C_5© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 05 — 17 November 200 of 23

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

7.5Bus transactions

Data is transmitted to the PCA9543A control register using the Write mode as shown inFigure13.

slave addressSDAS11100A1A00AXXXcontrol registerXXXB1B0APSTART conditionR/Wacknowledgefrom slaveacknowledgefrom slaveSTOP condition002aab182Fig 13.Write control registerData is read from PCA9543A using the Read mode as shown inFigure14.

slave addressSDAS11100A1A01AXXcontrol registerINT1INT0XXB1last byteB0NAPSTART conditionR/Wacknowledgefrom slaveno acknowledgefrom masterSTOP condition002aab183Fig 14.Read control registerPCA9543A_43B_43C_5© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 05 — 17 November 200810 of 23

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PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

8.Application design-in information

VDD = 2.7 V to 5.5 VVDD = 3.3 VV = 2.7 V to 5.5 Vsee note (1)SDASCLSDASCLINTRESETI2C/SMBus masterA1A0VSSSD0SC0INT0V = 2.7 V to 5.5 Vchannel 0PCA9543ASD1SC1INT1002aab184see note (1)channel 1(1)If the device generating the interrupt has an open-drain output structure or can be 3-stated, apull-up resistor is required.If the device generating the interrupt has a totempole output structure and cannot be 3-stated, apull-up resistor is not required.The interrupt inputs should not be left ﬂoating.Fig 15.Typical application9.Limiting values

Table 6.Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced toVSS (ground=0V).[1]SymbolVDDVIIIIOIDDISSPtotTstgTamb

[1]

Parametersupply voltageinput voltageinput currentoutput currentsupply currentground supply currenttotal power dissipationstorage temperatureambient temperature

ConditionsMin−0.5−0.5-----−60

Max+7.0+7.0±20±25±100±100400+150+85

UnitVVmAmAmAmAmW°C°C

operating−40

The performance capability of a high-performance integrated circuit in conjunction with its thermal

environment can create junction temperatures which are detrimental to reliability. The maximum junctiontemperature of this integrated circuit should not exceed 125°C.

Product data sheetRev. 05 — 17 November 200811 of 23

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

10.Static characteristics

Table 7.Static characteristics

VDD = 2.3V to 3.6V; VSS=0V; Tamb =−40°C to +85°C; unless otherwise speciﬁed.SeeTable8 on page13 for VDD = 4.5V to 5.5V.[1]SymbolSupplyVDDIDDIstbVPORVILVIHIOLILCiVILVIHILICi

Pass gateRon

ON-state resistance

VDD=3.0 to 3.6V; VO=0.4V;IO=15mA

VDD=2.3V to 2.7V; VO=0.4V;IO=10mA

Vo(sw)

switch output voltage

Vi(sw)=VDD=3.3V; Io(sw)=−100µAVi(sw)=VDD=3.0V to 3.6V;Io(sw)=−100µA

Vi(sw)=VDD=2.5V; Io(sw)=−100µAVi(sw)=VDD=2.5V to 2.7V;Io(sw)=−100µA

ILCioINT outputIOLIOH

[1][2]

Parametersupply voltagesupply currentstandby currentpower-on reset voltageLOW-level input voltageHIGH-level input voltageLOW-level output currentleakage currentinput capacitanceLOW-level input voltageHIGH-level input voltageinput leakage currentinput capacitance

ConditionsMin2.3

Typ-400.21.6-----9---1.611161.9-1.5--3--

Max3.610012.1+0.3VDD6--+110+0.3VDDVDD+0.5+133055-2.8-2.0+15-+100

UnitVµAµAVVVmAmAµApFVVµApFΩΩVVVVµApFmAµA

operatingmode;VDD=3.6V;noload;VI=VDD or VSS; fSCL=100kHzStandby mode; VDD=3.6V; noload;VI=VDDorVSS; fSCL=0kHznoload; VI=VDDorVSS

[2]

---−0.50.7VDD

Input SCL; input/output SDA

VOL=0.4VVOL=0.6VVI=VDDorVSSVI=VSS36−1-−0.50.7VDD

Select inputs A0, A1,INT0,INT1,RESETVI=VDD or VSSVI=VSS

−1-57-1.6-1.1−1-3-

leakage currentinput/output capacitanceLOW-level output currentHIGH-level output current

VI=VDDorVSSVI=VSSVOL=0.4V

For operation between published voltage ranges, refer to the worst-case parameter in both ranges.VDD must be lowered to 0.2V in order to reset part.

Product data sheetRev. 05 — 17 November 200812 of 23

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

Table 8.Static characteristics

VDD = 4.5V to 5.5V; VSS = 0V; Tamb =−40°C to +85°C; unless otherwise speciﬁed.SeeTable7 on page12 for VDD = 2.3V to 3.6V.[1]SymbolSupplyVDDIDD

supply voltagesupply current

Operating mode; VDD=5.5V;noload; VI=VDD or VSS;fSCL=100kHz

Standby mode; VDD=5.5V;noload; VI=VDDorVSS;fSCL=0kHz

noload; VI=VDDorVSS

[2]

ParameterConditionsMin4.5-

Typ-25

Max5.5100

UnitVµA

Istb

standby current-0.21µA

VPORVILVIHIOLILCiVILVIHILICi

Pass gateRonVo(sw)

power-on reset voltageLOW-level input voltageHIGH-level input voltageLOW-level output currentleakage currentinput capacitanceLOW-level input voltageHIGH-level input voltageinput leakage currentinput capacitanceon-state resistanceswitch output voltage

-−0.50.7VDD

1.7-----9---293.6--3--

2.1+0.3VDD6--+110+0.3VDDVDD+0.5+50524-4.5+1005-+100

VVVmAmAµApFVVµApFΩVVµApFmAµA

Input SCL; input/output SDA

VOL=0.4VVOL=0.6VVI=VDDorVSSVI=VSS36−1-−0.50.7VDD

Select inputs A0, A1,INT0 toINT3,RESETVI=VDD or VSSVI=VSS

VDD=4.5V to 5.5V; VO=0.4V;IO=15mAVi(sw)=VDD=5.0V;Io(sw)=−100µA

Vi(sw)=VDD=4.5V to 5.5V;Io(sw)=−100µA

−1-4-2.6−1-3-

ILCioINT outputIOLIOH

[1][2]

leakage currentinput/output capacitanceLOW-level output currentHIGH-level output current

VI=VDDorVSSVI=VSSVOL=0.4V

For operation between published voltage ranges, refer to the worst-case parameter in both ranges.VDD must be lowered to 0.2V in order to reset part.

Product data sheetRev. 05 — 17 November 200813 of 23

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PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

11.Dynamic characteristics

Table 9.SymbolDynamic characteristics

ParameterConditionsStandard-modeFast-mode I2C-busUnitI2C-busMintPDfSCLtBUFtHD;STAtLOWtHIGHtSU;STAtSU;STOtHD;DATtSU;DATtrtfCbtSPtVD;DATtVD;ACKINTtv(INTnN-INTN)td(INTnN-INTN)tw(rej)Ltw(rej)HRESETtw(rst)LtrsttREC;STA

[1][2][3][4][5]

Max0.3[1]100------3.45-10003004005010.6142-----

Min-01.30.61.30.60.60.60[3]10020+0.1Cb[4]20+0.1Cb[4]

-------10.545000

Max0.3[1]ns400------0.9-3003004005010.6142-----kHzµsµsµsµsµsµsµsnsnsµsµsnsµsµsµsµsµsµsµsnsnsns

propagation delaySCL clock frequency

bus free time between a STOP andSTART condition

holdtime(repeated)STARTconditionLOW period of the SCL clockHIGH period of the SCL clockset-up time for a repeated STARTcondition

set-up time for STOP conditiondata hold timedata set-up time

rise time of both SDA and SCLsignals

falltimeofbothSDAandSCLsignalscapacitive load for each bus linepulse width of spikes that must besuppressed by the input ﬁlterdata valid time

data valid acknowledge timevalid time fromINTn toINT signaldelay time fromINTn toINT inactiveLOW-level rejection timeHIGH-level rejection timeLOW-level reset timereset time

recovery time to START condition

from SDA to SDn,or SCL to SCn

-04.7

[2]

4.04.74.04.74.00[3]250----

HIGH-to-LOWLOW-to-HIGH

[5][5]

-----INTn inputsINTn inputs10.54

SDA clear5000

Pass gate propagation delay is calculated from the 20Ω typical Ron and the 15pF load capacitance.Hold time (repeated) START condition. After this period, the ﬁrst clock pulse is generated.

A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order tobridge the undeﬁned region of the falling edge of SCL.Cb=total capacitance of one bus line in pF.

Measurements taken with 1kΩ pull-up resistor and 50pF load.

Product data sheetRev. 05 — 17 November 200814 of 23

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NXP Semiconductors

PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

SDAtBUFtLOWSCLtrtftHD;STAtSPtHD;STAPStHD;DATtHIGHtSU;DATtSU;STASrtSU;STOP002aaa986Fig 16.Deﬁnition of timing on the I2C-busSTARTSCLACK or read cycleSDA30 %trstRESET50 %tREC;STA50 %50 %tw(rst)L002aac549Fig 17.Deﬁnition ofRESET timingprotocolSTARTcondition(S)tSU;STAbit 7MSB(A7)tLOWtHIGHbit 6(A6)bit 0(R/W)acknowledge(A)STOPcondition(P)1/fSCLSCLtBUFSDAtrtftHD;STAtSU;DATtHD;DATtVD;DATtVD;ACKtSU;STO002aab175Rise and fall times refer to VIL and VIH.Fig 18.I2C-bus timing diagramPCA9543A_43B_43C_5© NXP B.V. 2008. All rights reserved.

Product data sheetRev. 05 — 17 November 200815 of 23

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PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

12.Package outline

SO14: plastic small outline package; 14 leads; body width 3.9 mm

SOT108-1

DEAXcyHEvMAZ148QA2pin 1 indexθLp1ebp7wMLdetail XA1(A )3A02.5scale5 mmDIMENSIONS (inch dimensions are derived from the original mm dimensions)UNITmmAmax.1.75A10.250.10A21.451.25A30.250.01bp0.490.36c0.250.19D(1)8.758.55E(1)4.03.80.160.15e1.270.05HE6.25.8L1.05Lp1.00.4Q0.70.60.0280.024v0.250.01w0.250.01y0.10.004Z(1)0.70.30.0280.012θoinches0.069Note0.0100.0570.0040.0490.0190.01000.350.0140.00750.340.2440.0390.0410.2280.0168o01. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINEVERSION SOT108-1 REFERENCES IEC 076E06 JEDEC MS-012 JEITAEUROPEANPROJECTIONISSUE DATE99-12-2703-02-19Fig 19.Package outline SOT108-1 (SO14)

PCA9543A_43B_43C_5

Product data sheetRev. 05 — 17 November 200816 of 23

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PCA9543A/43B/43C

2-channel I2C-bus switch with interrupt logic and reset

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mmSOT402-1

DEAXcyHEvMAZ148QA2pin 1 index(A )3A1θLpLA1ebp7wMdetail X02.5scale5 mmDIMENSIONS (mm are the original dimensions)UNITmmAmax.1.1A10.150.05A20.950.80A30.25bp0.300.19c0.20.1D(1)5.14.9E(2)4.54.3e0.65HE6.66.2L1Lp0.750.50Q0.40.3v0.2w0.13y0.1Z(1)0.720.38θ8o0oNotes1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.OUTLINEVERSION SOT402-1 REFERENCES IEC JEDEC MO-153 JEITAEUROPEANPROJECTIONISSUE DATE99-12-2703-02-18Fig 20.Package outline SOT402-1 (TSSOP14)

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13.Soldering of SMD packages

Thistextprovidesaverybriefinsightintoacomplextechnology.Amorein-depthaccountof soldering ICs can be found in Application NoteAN10365 “Surface mount reﬂowsoldering description”.

13.1Introduction to soldering

Soldering is one of the most common methods through which packages are attached toPrintedCircuitBoards(PCBs),toformelectricalcircuits.Thesolderedjointprovidesboththe mechanical and the electrical connection. There is no single soldering method that isideal for all IC packages. Wave soldering is often preferred when through-hole and

Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is notsuitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and highdensities that come with increased miniaturization.

13.2Wave and reﬂow soldering

Wavesolderingisajoiningtechnologyinwhichthejointsaremadebysoldercomingfroma standing wave of liquid solder. The wave soldering process is suitable for the following:

•Through-hole components

•Leaded or leadless SMDs, which are glued to the surface of the printed circuit board

Not all SMDs can be wave soldered. Packages with solder balls, and some leadlesspackages which have solder lands underneath the body, cannot be wave soldered. Also,leaded SMDs with leads having a pitch smaller than ~0.6mm cannot be wave soldered,due to an increased probability of bridging.

The reﬂow soldering process involves applying solder paste to a board, followed bycomponent placement and exposure to a temperature proﬁle. Leaded packages,packages with solder balls, and leadless packages are all reﬂow solderable.Key characteristics in both wave and reﬂow soldering are:

••••••

Board speciﬁcations, including the board ﬁnish, solder masks and viasPackage footprints, including solder thieves and orientationThe moisture sensitivity level of the packagesPackage placementInspection and repair

Lead-free soldering versus SnPb soldering

13.3Wave soldering

Key characteristics in wave soldering are:

•Process issues, such as application of adhesive and ﬂux, clinching of leads, board

transport, the solder wave parameters, and the time during which components areexposed to the wave

•Solder bath speciﬁcations, including temperature and impurities

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13.4Reﬂow soldering

Key characteristics in reﬂow soldering are:

•Lead-freeversusSnPbsoldering;notethatalead-freereﬂowprocessusuallyleadsto

higher minimum peak temperatures (seeFigure21) than a SnPb process, thusreducing the process window

•Solder paste printing issues including smearing, release, and adjusting the process

window for a mix of large and small components on one board

•Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is

heated to the peak temperature) and cooling down. It is imperative that the peak

temperatureishighenoughforthesoldertomakereliablesolderjoints(asolderpastecharacteristic). In addition, the peak temperature must be low enough that thepackages and/or boards are not damaged. The peak temperature of the packagedepends on package thickness and volume and is classiﬁed in accordance withTable10 and11

Table 10.

SnPb eutectic process (from J-STD-020C)

Package reﬂow temperature (°C)Volume (mm3)< 350< 2.5≥ 2.5Table 11.

235220

Lead-free process (from J-STD-020C)

Package reﬂow temperature (°C)Volume (mm3)< 350< 1.61.6 to 2.5> 2.5

260260250

350 to 2000260250245

> 2000260245245

≥ 350220220

Package thickness (mm)Package thickness (mm)Moisture sensitivity precautions, as indicated on the packing, must be respected at alltimes.

Studies have shown that small packages reach higher temperatures during reﬂowsoldering, seeFigure21.

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temperaturemaximum peak temperature= MSL limit, damage levelminimum peak temperature= minimum soldering temperaturepeak temperaturetime001aac844MSL: Moisture Sensitivity LevelFig 21.Temperature proﬁles for large and small componentsFor further information on temperature proﬁles, refer to Application NoteAN10365“Surface mount reﬂow soldering description”.

14.Abbreviations

Table 12.AcronymCDMESDHBMICI2C-busLSBMMMSBPCBSMBus

Abbreviations

DescriptionCharged-Device ModelElectroStatic DischargeHuman Body ModelIntegrated Circuit

Inter-Integrated Circuit busLeast Signiﬁcant BitMachine ModelMost Signiﬁcant BitPrinted-Circuit BoardSystem Management Bus

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15.Revision history

Table 13.

Revision history

Release dateData sheet statusProduct data sheet

Change notice-SupersedesPCA9543A_43B_43C_4

Document IDModiﬁcations:

PCA9543A_43B_43C_520081117

••

Section 6.3 “RESET input”: changed symbol from “tWL” to “tw(rst)L”Table 9 “Dynamic characteristics”, sub-section “INT”:–symbol tw(rej)L: changed Unit from “ns” to “µs”

–symbol tw(rej)H: Min value (for both Standard-mode I2C-bus and Fast-mode I2C-bus)changed from “500ns” to “0.5µs”

PCA9543A_43B_43C_420061020PCA9543A_3(939775014316)PCA9543A_2(939775013988)PCA9543A_1(939775013299)

200503212004092920040728

Product data sheetProduct data sheetObjective data sheetObjective data sheet

----

PCA9543A_3PCA9543A_2PCA9543A_1-

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16.Legal information

16.1Data sheet status

Document status[1][2]Objective [short] data sheetPreliminary [short] data sheetProduct [short] data sheet

[1][2][3]

Product status[3]DevelopmentQualiﬁcationProduction

DeﬁnitionThis document contains data from the objective speciﬁcation for product development.This document contains data from the preliminary speciﬁcation.This document contains the product speciﬁcation.

Please consult the most recently issued document before initiating or completing a design.The term ‘short data sheet’ is explained in section “Deﬁnitions”.

Theproductstatusofdevice(s)describedinthisdocumentmayhavechangedsincethisdocumentwaspublishedandmaydifferincaseofmultipledevices.Thelatestproductstatusinformation is available on the Internet at URLhttp://www.nxp.com.

16.2Deﬁnitions

Draft —The document is a draft version only. The content is still underinternal review and subject to formal approval, which may result inmodiﬁcations or additions. NXP Semiconductors does not give anyrepresentations or warranties as to the accuracy or completeness of

informationincludedhereinandshallhavenoliabilityfortheconsequencesofuse of such information.

Short data sheet —A short data sheet is an extract from a full data sheetwiththesameproducttypenumber(s)andtitle.Ashortdatasheetisintendedforquickreferenceonlyandshouldnotbereliedupontocontaindetailedandfull information. For detailed and full information see the relevant full datasheet, which is available on request via the local NXP Semiconductors salesofﬁce. In case of any inconsistency or conﬂict with the short data sheet, thefull data sheet shall prevail.

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use ofNXP Semiconductors products in such equipment or applications andtherefore such inclusion and/or use is at the customer’s own risk.

Applications —Applications that are described herein for any of theseproducts are for illustrative purposes only. NXP Semiconductors makes norepresentation or warranty that such applications will be suitable for thespeciﬁed use without further testing or modiﬁcation.

Limiting values —Stress above one or more limiting values (as deﬁned intheAbsoluteMaximumRatingsSystemofIEC60134)maycausepermanentdamagetothedevice.Limitingvaluesarestressratingsonlyandoperationofthe device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limitingvalues for extended periods may affect device reliability.

Terms and conditions of sale —NXP Semiconductors products are soldsubjecttothegeneraltermsandconditionsofcommercialsale,aspublishedathttp://www.nxp.com/proﬁle/terms, including those pertaining to warranty,intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case ofany inconsistency or conﬂict between information in this document and suchterms and conditions, the latter will prevail.

No offer to sell or license —Nothing in this document may be interpretedor construed as an offer to sell products that is open for acceptance or thegrant,conveyanceorimplicationofanylicenseunderanycopyrights,patentsor other industrial or intellectual property rights.

16.3Disclaimers

General —Information in this document is believed to be accurate and

reliable.However,NXPSemiconductorsdoesnotgiveanyrepresentationsorwarranties,expressedorimplied,astotheaccuracyorcompletenessofsuchinformation and shall have no liability for the consequences of use of suchinformation.

Right to make changes —NXPSemiconductorsreservestherighttomakechanges to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and withoutnotice.Thisdocumentsupersedesandreplacesallinformationsuppliedpriorto the publication hereof.

Suitability for use —NXP Semiconductors products are not designed,authorized or warranted to be suitable for use in medical, military, aircraft,space or life support equipment, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

16.4Trademarks

Notice:Allreferencedbrands,productnames,servicenamesandtrademarksare the property of their respective owners.I2C-bus —logois a trademark of NXP B.V.

17.Contact information

For more information, please visit:http://www.nxp.com

For sales ofﬁce addresses, please send an email to:salesaddresses@nxp.com

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18.Contents

1General description. . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Ordering information. . . . . . . . . . . . . . . . . . . . . 23.1Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 24Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35Pinning information. . . . . . . . . . . . . . . . . . . . . . 45.1Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45.2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 46Functional description . . . . . . . . . . . . . . . . . . . 56.1Device address. . . . . . . . . . . . . . . . . . . . . . . . . 56.2Control register. . . . . . . . . . . . . . . . . . . . . . . . . 56.2.1Control register deﬁnition . . . . . . . . . . . . . . . . . 66.2.2Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . 66.3RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . . 76.4Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 76.5Voltage translation . . . . . . . . . . . . . . . . . . . . . . 77Characteristics of the I2C-bus. . . . . . . . . . . . . . 87.1Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87.2START and STOP conditions . . . . . . . . . . . . . . 87.3System conﬁguration . . . . . . . . . . . . . . . . . . . . 97.4Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . 97.5Bus transactions. . . . . . . . . . . . . . . . . . . . . . . 108Application design-in information . . . . . . . . . 119Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 1110Static characteristics. . . . . . . . . . . . . . . . . . . . 1211Dynamic characteristics . . . . . . . . . . . . . . . . . 1412Package outline . . . . . . . . . . . . . . . . . . . . . . . . 1613Soldering of SMD packages . . . . . . . . . . . . . . 1813.1Introduction to soldering. . . . . . . . . . . . . . . . . 1813.2Wave and reﬂow soldering . . . . . . . . . . . . . . . 1813.3Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 1813.4Reﬂow soldering. . . . . . . . . . . . . . . . . . . . . . . 1914Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 2015Revision history. . . . . . . . . . . . . . . . . . . . . . . . 2116Legal information. . . . . . . . . . . . . . . . . . . . . . . 2216.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . 2216.2Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 2216.4Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 2217Contact information. . . . . . . . . . . . . . . . . . . . . 2218

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Pleasebeawarethatimportantnoticesconcerningthisdocumentandtheproduct(s)described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 17 November 2008

Document identifier: PCA9543A_43B_43C_5

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