FM1608 Kb Bytewide FRAM Memory Features K bit Ferroelectric Nonvolatile RAM • Organized as 8,192 x 8 bits • High Endurance 1 Trillion (1012) Read/Writes • 45 year Data Retention • NoDelay™ Writes • Advanced High-Reliability Ferroelectric Process Superior to BBSRAM Modules • No battery concerns • Monolithic reliability • True surface mount solution, no rework steps • Superior for moisture, shock, and vibration • Resistant to negative voltage undershoots SRAM & EEPROM Compatible • JEDEC 8Kx8 SRAM & EEPROM pinout • 120 ns Access Time • 180 ns Cycle Time Low Power Operation • 15 mA Active Current • 20 µA Standby Current Industry Standard Configuration • Industrial Temperature -40° C to +85° C • 28-pin SOIC or DIP • “Green”/RoHS Packaging Pin Configuration NCA12A7A6A5A4A3A2A1A0DQ0DQ1DQ2VSS123456710111213142827262524232221201918171615Description The FM1608 is a -kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile but operates in other respects as a RAM. It provides data retention for 45 years while eliminating the reliability concerns, functional disadvantages and system design complexities of battery-backed SRAM. Its fast write and high write endurance make it superior to other types of nonvolatile memory. In-system operation of the FM1608 is very similar to other RAM based devices. Minimum read- and write-cycle times are equal. The FRAM memory, however, is nonvolatile due to its unique ferroelectric memory process. Unlike BBSRAM, the FM1608 is a truly monolithic nonvolatile memory. It provides the same functional benefits of a fast write without the serious disadvantages associated with modules and batteries or hybrid memory solutions. These capabilities make the FM1608 ideal for nonvolatile memory applications requiring frequent or rapid writes in a bytewide environment. The availability of a true surface-mount package improves the manufacturability of new designs, while the DIP package facilitates simple design retrofits. The FM1608 offers guaranteed operation over an industrial temperature range of -40°C to +85°C. VDDWENCA8A9A11OEA10CEDQ7DQ6DQ5DQ4DQ3 Ordering Information FM1608-120-PG 120 ns access, 28-pin “Green” DIP FM1608-120-SG 120 ns access, 28-pin “Green” SOIC This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Rev. 3.2 May 2007 1 of 12 FM1608 A10-A12Block DecoderA0-A12AddressLatchA0-A7RowDecoder8,192 x 8 FRAM ArrayCEA8-A9Column DecoderWEOEControlLogicI/O LatchBus DriverDQ0-7Figure 1. Block Diagram Pin Description Pin Name A0-A12 Pin Description Address: The 13 address inputs select one of 8,192 bytes in the FRAM array. The address value will be latched on the falling edge of /CE. DQ0-7 I/O Data: 8-bit bi-directional data bus for accessing the FRAM array. /CE Input Chip Enable: /CE selects the device when low. Asserting /CE low causes the address to be latched internally. Address changes that occur after /CE goes low will be ignored until the next falling edge occurs. /OE Input Output Enable: Asserting /OE low causes the FM1608 to drive the data bus when valid data is available. Deasserting /OE high causes the DQ pins to be tri-stated. /WE Input Write Enable: Asserting /WE low causes the FM1608 to write the contents of the data bus to the address location latched by the falling edge of /CE. VDD Supply Supply Voltage: 5V VSS Supply Ground. Functional Truth Table /CE /WE Function H X Standby/Precharge X Latch Address (and Begin Write if /WE=low) ↓ L H Read L Write ↓ Note: The /OE pin controls only the DQ output buffers.I/O Input Rev. 3.2 May 2007 2 of 12 FM1608 of FRAM technology including NoDelay writes and much higher write endurance. Read Operation A read operation begins on the falling edge of /CE. At this time, the address bits are latched and a memory cycle is initiated. Once started, a complete memory cycle must be completed internally regardless of the state of /CE. Data becomes available on the bus after the access time has been satisfied. After the address has been latched, the address value may change upon satisfying the hold time parameter. Unlike an SRAM, changing address values will have no effect on the memory operation after the address is latched. The FM1608 will drive the data bus when /OE is asserted low. If /OE is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is inactive the data bus will remain tri-stated. Write Operation Writes occur in the FM1608 within the same time interval as reads. The FM1608 supports both /CE- and /WE-controlled write cycles. In both cases, the address is latched on the falling edge of /CE. In a /CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the part begins the memory cycle as a write. The FM1608 will not drive the data bus regardless of the state of /OE. In a /WE-controlled write, the memory cycle begins on the falling edge of /CE. The /WE signal falls after the falling edge of /CE. Therefore the memory cycle begins as a read. The data bus will be driven according to the state of /OE until /WE falls. The timing of both /CE- and /WE-controlled write cycles is shown in the Electrical Specifications section. Write access to the array begins asynchronously after the memory cycle is initiated. The write access terminates on the rising edge of /WE or /CE, whichever is first. Data set-up time, as shown in the electrical specifications, indicates the interval during which data cannot change prior to the end of the write access. 3 of 12 OverviewThe FM1608 is a bytewide FRAM memory. The memory array is logically organized as 8,192 x 8 and is accessed using an industry standard parallel interface. The FM1608 is inherently nonvolatile via its unique ferroelectric process. All data written to the part is immediately nonvolatile with no delay. Functional operation of the FRAM memory is the same as SRAM type devices, except the FM1608 requires a falling edge of /CE to start each memory cycle. Memory Architecture Users access 8,192 memory locations each with 8 data bits through a parallel interface. The 13-bit address specifies each of the 8,192 bytes uniquely. Internally, the memory array is organized into 8 blocks of 1Kb each. The 3 most-significant address inputs decode one of 8 blocks. This block segmentation has no effect on operation, however the user may wish to group data into blocks by its endurance requirements as explained in a later section. The cycle time is the same for read and write memory operations. This simplifies memory controller logic and timing circuits. Likewise the access time is the same for read and write memory operations. When /CE is deasserted high, a precharge operation begins, and is required of every memory cycle. Thus unlike SRAM, the access and cycle times are not equal. Writes occur immediately at the end of the access with no delay. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. Note that the FM1608 has no special power-down demands. It will not block user access, and it contains no power-management circuits other than a simple internal power-on reset. It is the user’s responsibility to ensure that VDD is within datasheet tolerances and to ensure the proper voltage level and timing relationship between VDD and /CE in power-up and power-down events to prevent incorrect operation. Memory Operation The FM1608 is designed to operate in a manner very similar to other bytewide memory products. For users familiar with BBSRAM, the performance is comparable but the bytewide interface operates in a slightly different manner as described below. For users familiar with EEPROM, the obvious differences result from the higher write performance Rev. 3.2 May 2007 Unlike other truly nonvolatile memory technologies, there is no write delay with FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Therefore, any operation including read or write can occur immediately following a write. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Precharge Operation The precharge operation is an internal condition that prepares the memory for a new access. All memory cycles consist of a memory access and a precharge. The precharge is initiated by deasserting the /CE pin high. It must remain high for at least the minimum precharge time tPC. The user dictates the beginning of this operation since a precharge will not begin until /CE rises. However the device has a maximum /CE low time specification that must be satisfied. FM1608 located in different rows. Regardless, FRAM offers substantially higher write endurance than other nonvolatile memories. The rated endurance limit of 1012 cycles will allow 3000 accesses per second to the same row for 10 years. FRAM Design Considerations When designing with FRAM for the first time, users of SRAM will recognize a few minor differences. First, bytewide FRAM memories latch each address on the falling edge of chip enable. This allows the address bus to change after starting the memory access. Since every access latches the memory address on the falling edge of /CE, users cannot ground it as they might with SRAM. Users who are modifying existing designs to use FRAM should examine the memory controller for timing compatibility of address and control pins. Each memory access must be qualified with a low transition of /CE. In many cases, this is the only change required. An example of the signal relationships is shown in Figure 2 below. Also shown is a common SRAM signal relationship that will not work for the FM1608. The reason for /CE to strobe for each address is two-fold: it latches the new address and creates the necessary precharge period while /CE is high. Endurance The FM1608 internally operates with a read and restore mechanism. Therefore, each read and write cycle involves a change of state. The memory architecture is based on an array of rows and columns. Each read or write access causes an endurance cycle for an entire row. In the FM1608, a row is 32 bits wide. Every 4-byte boundary marks the beginning of a new row. Endurance can be optimized by ensuring frequently accessed data is Figure 2. Memory Address and /CE Relationships Rev. 3.2 May 2007 4 of 12 A second design consideration relates to the level of VDD during operation. Battery-backed SRAMs are designed to monitor VDD in order to switch to battery backup. They typically block user access below a certain VDD level in order to minimize battery drain from an otherwise active SRAM. The user can be abruptly cut off from access to the memory in a power down situation without warning. FRAM memories do not need this system overhead. The memory will not block access at any VDD level. The user, however, should prevent the processor from accessing memory when VDD is out-of-tolerance. The common design practice of holding a processor in reset during powerdown may be sufficient. It is recommended that Chip Enable is pulled high and allowed to track VDD during powerup and powerdown cycles. It is the user’s responsibility to ensure that chip enable is high to prevent accesses below VDD min. (4.5V). Figure 3 shows a pullup resistor on /CE FM1608 which will keep the pin high during power cycles assuming the MCU/MPU pin tri-states during the reset condition. The pullup resistor value should be chosen to ensure the /CE pin tracks VDD yet a high enough value that the current drawn when /CE is low is not an issue. VDD R MCU/MPU FM1608 CE WE OE A(12:0) DQ Figure 3. Use of Pullup Resistor on /CE Rev. 3.2 May 2007 5 of 12 FM1608 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +7.0V VIN Voltage on any pin with respect to VSS -1.0V to +7.0V and VIN < VDD+1.0V TSTG Storage Temperature -55°C to + 125°C TLEAD Lead temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage 4kV - Human Body Model (JEDEC Std JESD22-A114-B) 300V - Machine Model (JEDEC Std JESD22-A115-A) Package Moisture Sensitivity Level MSL-2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply 4.5 5.0 5.5 V IDD1 VDD Supply Current – Active 5 15 mA 1 ISB1 Standby Current – TTL 400 2 µA ISB2 Standby Current – CMOS 7 20 3 µA ILI Input Leakage Current 10 4 µA ILO Output Leakage Current 10 4 µA VIH Input High Voltage 2.0 VDD + 0.3 V VIL Input Low Voltage -0.3 0.8 V VOH Output High Voltage (IOH = -2.0 mA) 2.4 - V VOL Output Low Voltage (IOL = -4.2 mA) - 0.4 V Notes 1. VDD = 5.5V, /CE cycling at minimum cycle time. All inputs at CMOS levels, all outputs unloaded. 2. VDD = 5.5V, /CE at VIH, All other pins at TTL levels. 3. VDD = 5.5V, /CE at VIH, All other pins at CMOS levels. 4. VIN, VOUT between VDD and VSS. Data Retention (VDD = 4.5V to 5.5V unless otherwise specified) Parameter Min Units Notes Data Retention 45 Years Rev. 3.2 May 2007 6 of 12 FM1608 Read Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tCE Chip Enable Access Time ( to data valid) 120 ns tCA Chip Enable Active Time 120 2,000 ns tRC Read Cycle Time 180 ns tPC Precharge Time 60 ns tAS Address Setup Time 0 ns tAH Address Hold Time 10 ns tOE Output Enable Access Time 10 ns tHZ Chip Enable to Output High-Z 15 ns 1 tOHZ Output Enable to Output High-Z 15 ns 1 Write Cycle AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tCA Chip Enable Active Time 120 2,000 ns tCW Chip Enable to Write High 120 ns tWC Write Cycle Time 180 ns tPC Precharge Time 60 ns tAS Address Setup Time 0 ns tAH Address Hold Time 10 ns tWP Write Enable Pulse Width 40 ns tDS Data Setup 40 ns tDH Data Hold 0 ns tWZ Write Enable Low to Output High Z 15 ns 1 tWX Write Enable High to Output Driven 10 ns 1 tHZ Chip Enable to Output High-Z 15 ns 1 tWS Write Setup 0 ns 2 tWH Write Hold 0 ns 2 Notes 1 2 This parameter is periodically sampled and not 100% tested. The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. There is no timing specification associated with this relationship. Power Cycle Timing (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU VDD(min) to First Access Start 1 - µS tPD Last Access Complete to VDD(min) 0 - µS Rev. 3.2 May 2007 7 of 12 Capacitance (TA = 25° C , f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CI/O Input/Output Capacitance (DQ) 8 pF CIN Input Capacitance 6 pF AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels 0 to 3V Input rise and fall times 10 ns Input and output timing levels 1.5V Read Cycle Timing FM1608 /CE-Controlled Write Cycle Timing Rev. 3.2 May 2007 8 of 12 /WE-Controlled Write Cycle Timing FM1608 Power Cycle Timing VDDVDD (min)tPDtPCVIH (min)VDD (min)tPUCEVIH (min)VIL (max)Rev. 3.2 May 2007 9 of 12 28-pin SOIC (JEDEC MS-013 variation AE) All dimensions in millimeters FM1608 7.50 ±0.1010.30 ±0.30Pin 117.90 ±0.202.352.6545°0?- 8?1.27 typ0.330.510.100.300.100.250.750.230.320.401.27 SOIC Package Marking Scheme Legend: XXXX= part number, S=speed (-120), P= package type (-PG, -SG) RAMTRON R=rev code, YY=year, WW=work week, LLLLLL= lot code XXXXXXX-S-P RYYWWLLLLLLL Example: FM1608, 120ns speed, “Green” SOIC package, M rev., Year 2007, Work Week 11, Lot code 70085G RAMTRON FM1608-120-SG M071170085G Rev. 3.2 May 2007 10 of 12 28-pin DIP (JEDEC MS-011) All dimensions in inches FM1608 0.4850.580PIN 11.3801.5650.1250.1950.250 max0.015min.0.6000.6250.005min.0.100 BSC0.0300.0700.0140.0220.1150.2000.600 BSC0.700 max. DIP Package Marking Scheme Legend: XXXX= part number, S=speed (-120), P= package type (-PG, -SG) RAMTRON R=rev code, YY=year, WW=work week, LLLLLL= lot code XXXXXXX-S-P RYYWWLLLLLLL Example: FM1608, 120ns speed, “Green” DIP package, M rev., Year 2007, Work Week 11, Lot code 70085G RAMTRON FM1608-120-PG M071170085G Rev. 3.2 May 2007 11 of 12 FM1608 Revision History Revision 3.0 Date 11/16/04 Summary Removed Power Down Sequence diagram and associated timing parameters. Date codes 0435 and later are not affected by brownout conditions. Updated footer to comply with new Datasheet Change Procedure. Removed applications section. Removed -P and -S packaging options which are Not Recommended for New Designs. Extended data retention to 45 years. Added ESD and MSL ratings. Added recommendation on CE pin during power cycles. Redraw package outlines, added marking scheme. 3.1 10/3/06 3.2 5/30/07 Rev. 3.2 May 2007 12 of 12
