SA57A

Switching AmplifierFEATURES󰀠

♦ Low cost intelligent switching amplifier

♦ Directly connects to most embedded Micro-controllers and Digital Signal Controllers♦ Integrated gate driver logic with dead-time generation and shoot-through prevention♦ Wide power supply range (8.5V to 60V)♦ Over 15A peak output current per phase♦ 5A continuous output current per phase 8A continuous for A-Grade (SA57A)

♦ Independent current sensing for each output♦ User programmable cycle-by-cycle current limit protection

♦ Over-current and over-temperature warning signals

The SA57 is a fully integrated switching amplifier de-signed primarily to drive DC brush motors. Two inde-pendent half bridges provide over 15 amperes peak output current under microcontroller or DSC control. Thermal and short circuit monitoring is provided, which generates fault signals for the microcontroller to take appropriate action. A block diagram is provided in Fig-ure 1.

Additionally, cycle-by-cycle current limit offers user programmable hardware protection independent of the microcontroller. Output current is measured using an innovative low loss technique. The SA57 is built using a multi-technology process allowing CMOS logic con-trol and complementary DMOS output power devices on the same IC. Use of P-channel high side FETs en-ables 60V operation without bootstrap or charge pump circuitry.

The Power Quad surface mount package balances ex-cellent thermal performance with the advantages of a low profile surface mount package.

APPLICATIONS

♦ Bidirectional DC brush motors♦ 2 unidirectional DC brush motors♦ 2 independent solenoid actuators♦ Stepper motors

FIgURE󰀠󰀱.󰀠BLOCK󰀠DIAgRAm

VS+VDDVs1SCTEMPILIM/DIS1I1I2I1'I2'Vs2VDDVDDFaultLogicI1'I2'DIS21t1bPWMSignals2t2bSGNDGateControlPhase1Out1Out2ControlLogicPhase2SA57SwitchingAmplifierPGND 1GNDPGND 2SA57U󰀠󰀠http://www.cirrus.com

󰀠󰀠󰀠

󰀠Copyright © Cirrus Logic, Inc. 2008󰀠

(All Rights Reserved)

OCT󰀠2008󰀱󰀠

APEX − SA57UREVA

SA57ProductInnovationFrom󰀱.󰀠ChARACTERISTICS󰀠AND󰀠SPECIFICATIONS

NOTES: 1. (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Condi-tions. Typical performance characteristics and specifications are derived from measurements taken

at typical supply voltages and TC = 25°C).

ABSOLUTE󰀠mAxImUm󰀠RATINgS

Parameter

SUPPLY VOLTAGESUPPLY VOLTAGELOGIC INPUT VOLTAGEOUTPUT CURRENT, peak, 10ms2POWER DISSIPATION, avg, 25ºC2TEMPERATURE, junction3

TEMPERATURE RANGE, storageOPERATING TEMPERATURE, case

IOUTPDTJTSTGTA−55−40

VSVDD(-0.5)

Symbolminmax

605.5(VDD+0.5)

17100150125125

Units

VVVAW°C°C°C

2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power dissipation to achieve high MTBF.

3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed the specified current rating or a junction temperature of 150°C.

SA57

min

Typ

max

1

1.8

0.3

3.7

50

*

*

*

*

SPECIFICATIONS

Parameter

LOgICINPUT LOWINPUT HIGHOUTPUT LOWOUTPUT HIGHOUTPUT CURRENT(SC, Temp, ILIM/DIS1)POWER󰀠SUPPLYVSVS UNDERVOLTAGELOCKOUT, (UVLO)VDDSUPPLY CURRENT, VS

20 kHz (One phase switching at 50% duty cycle) , VS=50V, VDD=5V20 kHz (One phase switching at 50% duty cycle) , VS=50V, VDD=5V

4.5

25

UVLO

509

5.530

*

*

60

*

55***

VVVmA

*

VVVVmA

Test󰀠Conditions2

SA57A

min

Typ

max

Units

SUPPLY CURRENT, VDD

56**mA

* The specification of SA57A is identical to the specification for SA57 in applicable column to the left.

2󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠SA57U

ProductInnovationFromSA57SPECIFICATIONS,󰀠continued

Parameter

CURRENT󰀠LImITCURRENT LIMITTHRESHOLD (Vth)Vth HYSTERESISOUTPUT

CURRENT, CONTINUOUSRISING DELAY, TD (RISE)FALLING DELAY, TD (FALL)DISABLE DELAY, TD (DIS)ENABLE DELAY, TD (DIS)RISE TIME, T (RISE)FALL TIME, T (FALL)ON RESISTANCE

SOURCING (P-CHANNEL)ON RESISTANCE

SINKING (N-CHANNEL)ThERmAL

THERMAL WARNINGTHERMAL WARNINGHYSTERESIS

RESISTANCE, junction to case

TEMPERATURE RANGE, case

Full temperature rangeMeets Specifications

-25

135401.25

1.585

-40

***

*125

ºCºCºC/WºC

25ºC Case TemperatureSee Figure 10See Figure 10See Figure 10See Figure 10See Figure 11See Figure 115A Load5A Load

5

2702702002005050300250

750750

8

******300250

600600

AnsnsnsnsnsnsmΩmΩ

3.95100

**

VmV

Test󰀠Conditions2

SA57

min

Typ

max

min

SA57ATyp

max

Units

FIgURE󰀠2.󰀠-PIN󰀠QFP,󰀠PACKAgE󰀠STYLE󰀠hQ

SA57U󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀳󰀠

SA57VS SUPPLY CURRENTVS SUPPLY CURRENT (mA)ProductInnovationFrom25VS SUPPLY CURRENT (mA)2015105010

1801601201008060402000140VS SUPPLY CURRENT

10LOAD CURRENT (A)CURRENT SENSE

125°C25°C1

ONE PHASE SWITCHINGFREQUENCY = 20kHz50% DUTY CYCLE20304050VS SUPPLY VOLTAGE (V)60

ONE PHASE SWITCHING @50% DUTY CYCLE; VS=50V50100150200250300FREQUENCY (kHz)

0.10.01

0.11

SENSE CURRENT (mA)

10

8VDD SUPPLY CURRENT (mA)7.576.565.554.5410

VDD SUPPLY CURRENTVDD SUPPLY CURRENT (mA)ONE PHASE SWITCHINGFREQUENCY = 20kHz50% DUTY CYCLE54.94.84.74..50

VDD SUPPLY CURRENTPOWER DISSIPATION, PD120100

POWER DERATINGSA57A806040200-40

04080120CASE TEMPERATURE, TC

SA57125°C25°CONE PHASE SWITCHING @50% DUTY CYCLE; VS=50V50

100150200250300FREQUENCY (kHz)

20304050VS SUPPLY VOLTAGE (V)

60

0.80.75(N-Channel)0.70.650.60.55VS=110.5VS=130.45VS=150.40.35VS=170.30.250.2VS>220.150123456710

IOUT,(A)

ON RESISTANCE - BOTTOM FET0.8

0.75(P-Channel)0.70.650.6

VS=110.55

VS=130.5

0.45VS=150.40.350.3

VS>170.25

0.20.15

0123456710

IOUT,(A)

ON RESISTANCE - TOP FETRDS(on),(Ω)RDS(on),(Ω)DIODE FORWARD VOLTAGE - BOTTOM FET 54CURRENT (A)32100.5CURRENT (A)(N-Channel)543210DIODE FORWARD VOLTAGE - TOP FET (P-Channel)0.70.91.11.3FORWARD VOLTAGE (V)1.50.50.70.91.11.3FORWARD VOLTAGE (V)1.54󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠SA57U

ProductInnovationFromSA57FIgURE󰀠󰀳.󰀠ExTERNAL󰀠CONNECTIONS

PGND 1PGND 1PGND 1PGND 1OUT 2OUT 2OUT 135OUT 134OUT 133323130292827VS 2VS 2VS 2VS 2NCNCNCNCNCNCNC365251504948474544434241403938OUT 2NCPGND 2PGND 2PGND 2

HS

53545556575837NCVS 1VS 1VS 1NCHS

HSNC2bNC2tNC

596061626310121314151617181911123456726252423222021HSTEMPNCDIS2NCI1

I2ILIM/DIS1SCSGNDSGNDSGNDSGND1tVDDNCNCNCNCNCNCNC1bNCNCTABLE󰀠󰀱.󰀠PIN󰀠DESCRIPTIONSPin󰀠#29,30,3151,52,5355,56,573616317

Pin󰀠NameVS (phase 1) OUT 2

PGND (phase 2)SC2b2tI2ILIM/DIS1

Signal󰀠TypePower

Power OutputPower

Logic OutputLogic InputLogic InputAnalog Output

Simplified Pin DescriptionHigh Voltage Supply (8.5-60V) supplies phase 1 onlyHalf Bridge 2 Power Output

High Current GND Return Path for Power Output 2

Indication of a short of an output to supply, GND or another phase Logic high commands 2 phase lower FET to turn on Logic high commands 2 phase upper FET to turn on Phase 2 current sense output

As an output, logic high indicates cycle-by-cycle current limit, and logic low indicates normal operation. As an input, logic high places

Logic Input/Output

all outputs in a high impedance state and logic low disables the cycle-by-cycle current limit function.

SA57U󰀠󰀠󰀠󰀠󰀠󰀠󰀠

NC5󰀠

SA57TABLE󰀠󰀱.󰀠PIN󰀠DESCRIPTIONSPin󰀠#5,9,11,13151719212325

46,47,48,4933,34,3537,38,39,4026,27,58,592,4,6,8,10,12,14,16,18,20,22,24,28,32,36,41,42,43,44,45,50,54,60,62,ProductInnovationFromPin󰀠NameSGND1b1tVDDI1DIS2TEMP

VS (phase 2)OUT 1

PGND (phase 1)HS

Signal󰀠TypePower

Logic InputLogic InputPower

Analog OutputLogic InputLogic OutputPower

Power OutputPower

Mechanical

Simplified Pin DescriptionAnalog and digital GND – internally connected to PGNDLogic high commands 1 phase lower FET to turn on Logic high commands 1 phase upper FET to turn on Logic Supply (5V)

Phase 1 current sense output

Logic high places all outputs in a high impedance stateThermal indication of die temperature above 135ºCHigh Voltage Supply phase 2Half Bridge 1 Power Output

High Current GND Return Path for Power Outputs 1&2Pins connected to the package heat slug

NC---Do Not Connect

󰀱.2󰀠Pin󰀠Descriptions

VS:󰀠Supply voltage for the output transistors. These pins require decoupling (1μF capacitor with good high frequency characteristics is recommended) to the PGND pins. The decoupling capacitor should be located as close to the VS and PGND pins as possible. Additional capacitance will be required at the VS pins to handle load current peaks and potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding bypass capacitor selection. Note that Vs pins 29-31 carry only the phase 1 supply current. Pins 46-49 carry supply current for phase2. Phase 1 may be operated at a different supply voltage from phase 2. Only the B & C supply pins (46-49) are monitored for undervoltage conditions.

OUT󰀠󰀱,󰀠OUT󰀠2:󰀠These pins are the power output connections to the load. NOTE: When driving an inductive load, it is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)

PgND:󰀠Power Ground. This is the ground return connection for the output FETs. Return current from the load flows through these pins. PGND is internally connected to SGND through a resistance of a few ohms. See section 2.1 of this datasheet for more details.

SC:󰀠Short Circuit output. If a condition is detected on any output which is not in accordance with the input com-mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately 200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high state on the SC output will not automatically disable the device. The SC pin includes an internal 12kΩ series resis-tor.

󰀱b,󰀠2b:󰀠These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower N-channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side N-channel FET off. If 1b or 2b is high at the same time that a corresponding 1t or 2t input is high, protection circuitry will turn off both FETs in order to prevent shoot-through current on that output phase. Protection circuitry also in-

6󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠SA57U

ProductInnovationFromSA57cludes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching of the top and bottom input signals.

󰀱t,󰀠2t:󰀠These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper P-channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-channel FET off.

I󰀱,󰀠I2:󰀠Current sense pins. The SA57 supplies a positive current to these pins which is proportional to the current flowing through the top side P-channel FET for that phase. Commutating currents flowing through the back-body diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins. Nor do currents flowing through the low side N-channel FET, in either direction, register at the current sense pins. A resistor connected from a current sense pin to SGND creates a voltage signal representation of the phase current that can be monitored with ADC inputs of a processor or external circuitry.

The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this func-tionality are described in the applications section of this datasheet.

ILIm/DIS󰀱: This pin is directly connected to the disable circuitry of the SA57. Pulling this pin to logic high places OUT 1 and OUT 2 in a high impedance state. This pin is also connected internally to the output of the current limit latch through a 12kΩ resistor and can be monitored to observe the function of the cycle-by-cycle current limit feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.

SgND:󰀠This is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry is referenced to this pin. PGND is internally connected to GND through a resistance of a few ohms,. However, it is highly recommended to connect the GND pin to the PGND pins externally as close to the device as possible. Failure do to this may result in oscillations on the output pins during rising or falling edges.

VDD:󰀠This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the SA57. This pin requires decoupling (at least 0.1µF capacitor with good high frequency characteristics is recom-mended) to the SGND pin.

DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT 1 and OUT 2 in a high impedance state when pulled high. DIS2 has an internal 12kΩ pull-down resistor and may therefore be left unconnected.

TEmP:󰀠This logic level output goes high when the die temperature of the SA57 reaches approximately 135ºC. This pin WILL NOT automatically disable the device. The TEMP pin includes a 12kΩ series resistor.

hS:󰀠These pins are internally connected to the thermal slug on the reverse of the package. They should be con-nected to GND. Neither the heat slug nor these pins should be used to carry high current.NC:󰀠These “no-connect” pins should be left unconnected.

SA57U󰀠󰀠󰀠󰀠󰀠󰀠󰀠7󰀠

SA572.󰀠SA57󰀠OPERATION

ProductInnovationFromThe SA57 is designed primarily to drive DC brush motors. However, it can be used for any application requiring two high current outputs. The signal set of the SA57 is designed specifically to interface with a DSP or microcontroller. A typical system block diagram is shown in the figure below. Over-temperature, Short-Circuit and Current Limit fault signals provide important feedback to the system controller which can safely disable the output drivers in the pres-ence of a fault condition. High side current monitors for both phases provide performance information which can be used to regulate or limit torque.

FIgURE󰀠4.󰀠SYSTEm󰀠DIAgRAm

VDDSCTEMPILIM/DIS1Vs +Vs 1Vs 2FaultLogicCurrentI1monitorSignalsI2GNDDIS21t1bPWMSignals2t2bSGNDDC BRUSHMOTORControlLogicGateControl12OUT 1OUT 2Microcontrolleror DSCSA57 Switching AmplifierPGND 1SGNDGNDPGND 28󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠SA57U

ProductInnovationFromSA57The block diagram in Figure 5 illustrates the features of the input and output structures of the SA57. For simplicity, a single phase is shown.

FIgURE󰀠5.󰀠INPUT󰀠AND󰀠OUTPUT󰀠STRUCTURES󰀠FOR󰀠A󰀠SINgLE󰀠PhASE

12kSCLogicVddI1'12k+__TempSenseRefVthCurrentSenseSCILIM/DIS1I112kLim 1Lim 2UVLODIS212k1tGateControl1bPGNDOUT 1VsSGNDTABLE󰀠2.󰀠TRUTh󰀠TABLEILIM/DIS1OUT 1OUT 21b, 2b1t, 2tI1, I2DIS2Comments

00110X1XX>VthXXXXXXXX

XXXX

Top and Bottom output FETs for that phase are turned off.Bottom output FET for that phase is turned on.Top output FET for that phase is turned on.Both output FETs for that phase are turned off.

Voltage on I1 or I2 has exceeded Vth, which causes ILIM/DIS1 to go high.

1XHigh-Z

This internally disables Top and Bottom output FETs for ALL phases.

X1High-ZDIS2 pin pulled high, which disables all outputs.Pulled Pulling the ILIM/DIS1 pin high externally acts as a second disable input,

XHigh-Z

Highwhich disables ALL output FETs.

Determined Pulling the DIS2 pin low externally disables the cycle-by-cycle current limit

Pulled

0by PWM function. The state of the outputs is strictly a function of the PWM inputs.

Low

inputs

XXHigh-ZIf VS is below the UVLO threshold all output FETs will be disabled.

X00XX00XHigh-ZPGNDVSHigh-Z

SA57U󰀠󰀠󰀠󰀠󰀠󰀠󰀠

+TEMP󰀹󰀠

SA572.󰀱󰀠LAYOUT󰀠CONSIDERATIONS

ProductInnovationFromOutput traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing ensures normal operation. Poor routing and bypassing can cause erratic and low efficiency operation as well as ringing at the outputs.

The VS supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the VS pins. Total inductance of the routing from the capacitor to the VS and GND pins must be kept to a minimum to pre-vent noise from contaminating the logic control signals. A low ESR capacitor of at least 25μF per ampere of output current should be placed near the SA57 as well. Capacitor types rated for switching applications are the only types that should be considered.

The bypassing requirements of the VDD supply are less stringent, but still necessary. A 0.1μF to 0.47μF surface mount ceramic capacitor (X7R or NPO) connected directly to the VDD pin is sufficient.

SGND and PGND pins are connected internally. However, these pins must be connected externally in such a way that there is no motor current flowing in the logic and signal ground traces as parasitic resistances in the small signal routing can develop sufficient voltage drops to erroneously trigger input transitions. Alternatively, a ground plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This isolates noise between signal and power ground traces and prevents high currents from passing between the plane sections.

Unused area on the top and bottom PCB planes should be filled with solid or hatched copper to minimize inductive coupling between signals. The copper fill may be left unconnected, although a ground plane is recommended.

2.2󰀠FAULT󰀠INDICATIONS󰀠

In the case of either an over-temperature or short circuit fault, the SA57 will take no action to disable the outputs. Instead, the SC and TEMP signals are provided to an external controller, where a determination can be made re-garding the appropriate course of action. In most cases, the SC pin would be connected to a FAULT input on the processor, which would immediately disable its PWM outputs. The TEMP fault does not require such an immediate response, and would typically be connected to a GPIO, or Keyboard Interrupt pin of the processor. In this case, the processor would recognize the condition as an external interrupt, which could be processed in software via an Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of the disable inputs on the SA57.

Figure 6 shows an external SR flip-flop which pro-vides a hard wired shutdown of all outputs in re-sponse to a fault indication. An SC or TEMP fault sets the latch, pulling the disable pin high. The processor clears the latched condition with a GPIO. This circuit can be used in safety critical applications to remove software from the fault-shutdown loop, or simply to reduce processor overhead.

FIgURE󰀠6.󰀠ExTERNAL󰀠FAULT󰀠LATCh󰀠CIRCUITPWMSA57PROCESSORDIS2SCTEMPGPIOIn applications which may not have available GPIO,

the TEMP pin may be externally connected to the LATCHEDFAULTINTERRUPTadjacent DIS1 pin. If the device temperature reach-es ~135ºC all outputs will be disabled, de-energizing

the motor. The SA57 will re-energize the motor when the device temperature falls below approximately 95ºC. The TEMP pin hysteresis is wide to reduce the likelihood of thermal oscillations which can greatly reduce the life of the device.

FAULTRESET2.3 UNDER-VOLTAGE LOCKOUT

The undervoltage lockout condition results in the SA57 unilaterally disabling all output FETs until VS is above the UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lockout con-dition is in progress. The SA57 has two VS connections: one for phase 1 and another for phase 2. The supply volt-

󰀱0󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠SA57U

ProductInnovationFromSA57FiGURE 7. START-UP VOLTAGE AND CURRENT

NON-LIMITEDMOTORCURRENT

NON-LIMITEDBACK EMF

ages on these pins need not be the same, but the UVLO will engage if either is below the threshold. Hysteresis on the UVLO circuit prevents oscilla-tions with typical power supply variations.

2.4󰀠CURRENT󰀠SENSE

External power shunt resistors are not required with the SA57. Forward current in each top, P-LIMITEDBACKEMF

channel output FET is measured and mirrored to the respective current sense output pin, I1 and I2. By connecting a resistor between each cur-rent sense pin and a reference, such as ground, LIMITEDMOTORCURRENTa voltage develops across the resistor that is pro-portional to the output current for that phase. An ADC can monitor the voltages on these resistors for protection or for closed loop torque control in some application configurations. The current sense pins source current from the VDD supply. Headroom required for the current sense circuit is TIMEapproximately 0.5V. The nominal scale factor for

each proportional output current is shown in the typical performance plot on page 4 of this datasheet.

2.5󰀠CYCLE-BY-CYCLE󰀠CURRENT󰀠LImIT

In applications where the current in the motor is not directly controlled, both the average current rating of the motor and the inrush current must be considered when selecting a proper amplifier. For example, a 1A continuous motor might require a drive amplifier that can deliver well over 10A peak in order to survive the inrush condition at start-up.

Because the output current of each upper output FET is measured, the SA57 is able to provide a very robust current limit scheme. This enables the SA57 to safely and easily drive virtually any DC brush motor through a start-up inrush condition. With limited current, the starting torque and acceleration are also limited. The plot in Figure 7 shows starting current and back EMF with and without current limit enabled.

If the voltage of any of the two current sense pins exceeds the current limit threshold voltage (Vth), all outputs are disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase’s top side input goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal (1t or 2t). With most commutation schemes, the current limit will reset each PWM cycle. This scheme regulates the peak current in each phase during each PWM cycle as illustrated in the timing diagram below. The ratio of average to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the width of the pulse.

Figure 8 illustrates the current limit trigger and reset sequence. Current limit engages and ILIM/DIS1 goes high when any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth threshold is asynchronous with respect to the input PWM signal. The difference between the PWM period and the motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscilla-tion. This oscillation can be seen on the ILIM/DIS1 pin waveform in Figure 8.

Input signals commanding 0% or 100% duty cycle may be incompatible with the current limit feature due to the absence of rising edges of 1t and 2t. At high RPM, this may result in poor performance. At low RPM, the motor may stall if the current limit trips and the motor current reaches zero without a commutation edge which will typically reset the current limit latch.

SA57U󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀱󰀱󰀠

SA57The current limit feature may be disabled by tying the ILIM/DIS1 pin to GND. The current sense pins will continue to provide top FET output current information.Typically, the current sense pins source current into grounded resistors which pro-vide voltages to the current limit compara-tors. If instead the current limit resistors are connected to a voltage output DAC, the current limit can be controlled dynamically from the system controller. This technique essentially reduces the current limit thresh-old voltage to (Vth-VDAC). During expect-ed conditions of high torque demand, such as start-up or reversal, the DAC can adjust the current limit dynamically to allow pe-riods of high current. In normal operation when low current is expected, the DAC output voltage can increase, reducing the current limit setting to provide more con-servative fault protection.

ProductInnovationFromFiGURE 8. CURRENT LimiT WAVEFORmS

It INPUTVthI1OUT 1ILIM/DIS12.6󰀠ExTERNAL󰀠FLYBACK󰀠DIODES

External fly-back diodes will offer superior reverse recovery characteristics and lower forward voltage drop than the internal back-body diodes. In high current applications, external flyback diodes can reduce power dissipation and heating during commutation of the motor current. Reverse recovery time and capacitance are the most important parameters to consider when selecting these diodes. Ultra-fast rectifiers offer better reverse recovery time and Schottky diodes typically have low capacitance. Individual appli-cation requirements will be the guide when determining the need for these diodes and for selecting the component which is most suitable.

FIgURE󰀠󰀹.󰀠SChOTTKY󰀠DIODES

VSOUT 1VSSA57OUT 2󰀱2󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠SA57U

ProductInnovationFromSA57FIgURE󰀠󰀱0.󰀠TImINg󰀠DIAgRAmS

TOP INPUT

BOTTOM INPUT

DISABLE

OUTPUT

DELAY TIMINGtd(fall)td(rise)td(dis)td(dis)td(dis)td(dis)󰀳.󰀠POWER󰀠DISSIPATION

The thermally enhanced package of the SA57 al-lows several options for managing the power dis-sipated in the two output stages. Power dissipation in traditional PWM applications is a combination of output power dissipation and switching losses. Output power dissipation depends on the quadrant of operation and whether external flyback diodes are used to carry the reverse or commutating cur-rents. Switching losses are dependent on the fre-quency of the PWM cycle as described in the typi-cal performance graphs.

FIgURE󰀠󰀱󰀱.󰀠OUTPUT󰀠RESPONSE

80%

OUTPUT

20%

The size and orientation of the heatsink must be selected to manage the average power dissipation t(rise)t(fall)of the SA57. Applications vary widely and various thermal techniques are available to match the re-TOP INPUTquired performance. The patent pending mounting

technique shown in Figure 12, with the SA57 in-verted and suspended through a cutout in the PCB BOTTOM INPUTis adequate for power dissipation up to 17W with the HS33, a 1.5 inch long aluminum extrusion with

four fins. In free air, mounting the PCB perpendicular to the ground, such that the heated air flows upward along the channels of the fins can provide a total ΘJA of less than 14 ºC/W (9W max average PD). Mounting the PCB parallel to the ground impedes the flow of heated air and provides a ΘJA of 16.66 ºC/W (7.5W max average PD). In applica-tions in which higher power dissipation is expected or lower junction or case temperatures are required, a larger heatsink or circulated air can significantly improve the performance.

4.󰀠ORDERINg󰀠AND󰀠PRODUCT󰀠STATUS󰀠INFORmATIONMODELSA57-IHZSA57A-FHZ

TEMPERATURE-25 to 85ºC-40 to +125ºC

PACKAGE

pin Power QFP (HQ package drawing) pin Power QFP (HQ package drawing)

PRODUCTION STATUSSamples AvailableSamples Available

SA57U󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀱󰀳󰀠

SA57FIgURE󰀠󰀱2.󰀠hEATSINK󰀠TEChNIQUE

ProductInnovationFromPATENT󰀠PENDINg󰀠

CONTACTINg󰀠CIRRUS󰀠LOgIC󰀠SUPPORT

For all Apex Precision Power product questions and inquiries, call toll free 800-546-2739 in North America. For inquiries via email, please contact tucson.support@cirrus.com.

International customers can also request support by contacting their local Cirrus Logic Sales Representative.To find the one nearest to you, go to www.cirrus.com

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (\"Cirrus\") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided \"AS IS\" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con-sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP-ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PROD-UCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUS-TOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs, Apex and Apex Precision Power are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

󰀱4󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠󰀠SA57U