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专利名称：Data processing system and image
processing system
发明人：Satoh, Jun,Yamagishi, Kazushige,Nakashima,
Keisuke,Katsura, Koyo,Miyamoto,
Takashi,Watabe, Mitsuru,Ohmura, Kenichiroh
申请号：EP94115140.9申请日：19940926公开号：EP09100A3公开日：19970226
专利附图：
摘要：A data processor comprises a bus control circuit (14) adapted to be interfaced
with a synchronous DRAM (22) which can be accessed in synchronism with a clock signal(CLK), a plurality of data processing modules (12, 13) coupled to said bus control circuit(14) for producing data and addresses for accessing a memory (22), and a clock driver (16)for feeding intrinsic operation clocks to said data processing modules (12, 13) and forfeeding the clock signal for accessing said memory (22) in synchronism with theoperations of said data processing modules (12, 13) to be operated by the operationclock signals, to the outside.
申请人：HITACHI, LTD.
地址：6, Kanda Surugadai 4-chome Chiyoda-ku, Tokyo 100 JP
国籍：JP
代理机构：Strehl Schübel-Hopf Groening & Partner
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