ADC11DV200 Dual 11-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs
Literature Number: SNAS477
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C11DV200 Dual 11-bit, 200 MSPS Low-Power A/D Converter with Parallel OutputsADC11DV200
Dual 11-bit, 200 MSPS Low-Power A/D Converter withParallel LVDS/CMOS Outputs
General Description
The ADC11DV200 is a monolithic analog-to-digital convertercapable of converting two analog input signals into 11-bit dig-ital words at rates up to 200 Mega Samples Per Second(MSPS). The digital output mode is selectable and can be ei-ther differential LVDS or CMOS signals. This converter usesa differential, pipelined architecture with digital error correc-tion and an on-chip sample-and-hold circuit to minimize diesize and power consumption while providing excellent dy-namic performance. A unique sample-and-hold stage yieldsa full-power bandwidth of 900MHz. Fabricated in core CMOSprocess, the ADC11DV200 may be operated from a single1.8V power supply. The ADC11DV200 achieves approxi-mately 10.06 effective bits at Nyquist and consumes just280mW at 170MSPS in CMOS mode 450mW at 200MSPS inLVDS mode. The power consumption can be scaled downfurther by reducing sampling rates.
Features
■■■■■■■■■■
Single 1.8V power supply operation.Power scaling with clock frequency.Internal sample-and-hold.Internal or external reference.Power down mode.
Offset binary or 2's complement output data format.LVDS or CMOS output signals.
60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)Clock Duty Cycle Stabilizer.
IF Sampling Bandwidth > 900MHz.
Key Specifications
■■■■■■■■■
Resolution11 BitsConversion Rate200 MSPSENOB10.06 bits (typ) @Fin=70MHzSNR62.5 dBFS (typ) @Fin=70MHzSINAD62.3 dBFS (typ) @Fin=70MHzSFDR82 dBFS (typ) @Fin=70MHzLVDS Power450 mW (typ) @Fs=200 MSPSCMOS Power280 mW (typ) @Fs=170 MSPSOperating Temp. Range−40°C to +85°C.
Applications
■
■■■■
Digital Predistortion (DPD)
Wireless Communications InfrastructureMedical Imaging
Portable InstrumentationDigital Video
Block Diagram
30087502
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ADC1130087501
Ordering Information
Industrial (−40°C ≤ TA ≤ +85°C)
ADC11DV200CISQADC11DV200CISQEADC11DV200EB
Package60 Pin LLP60 Pin LLP,
250 pc. Tape and ReelEvaluation Board
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11DV200Pin No.ANALOG I/O
133
SymbolVINA+VINB+
Equivalent CircuitDescription
142
VINA-VINB-
Differential analog input pins. The differential full-scale inputsignal level is 1.5VP-P with each input pin signal centered ona common mode voltage, VCM.
106115
VRPAVRPBVRMAVRMBVRNAVRNB
97
These pins should each be bypassed to AGND with a low ESL(equivalent series inductance) 0.1 µF capacitor placed veryclose to the pin to minimize stray inductance. An 0201 size 0.1µF capacitor should be placed between VRP and VRN as closeto the pins as possible.
VRP and VRN should not be loaded. VRM may be loaded to 1mAfor use as a temperature stable 0.9V reference.
It is recommended to use VRM to provide the common modevoltage, VCM for the differential analog inputs.
Reference Voltage select pin and external reference input.The relationship between the voltage on the pin and thereference voltage is as follows:
The internal 0.75V reference is1.4V ≤ VREF ≤ VA
used.
The external reference voltage is0.2V ≤ VREF ≤ 1.4V
used.
Note: When using an externalreference, be sure to bypass witha 0.1µF capacitor to AGND asclose to the pin as possible.The internal 0.5V reference isAGND ≤ VREF ≤ 0.2V
used.
17
VREF
19
REXT
Programming resistor for analog bias current. Nominally a3.3kΩ to AGND for 200MSPS, or tie to VA to use the internalfrequency scaling current.
20DF/DCS
Data Format/Duty Cycle Correction selection pin.(see Table 1)
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ADC11DIGITAL I/O
5756CLK +CLK -
Clock input pins signal. The analog inputs are sampled orising edge of this signal. The clock can be configured fosingle-ended mode by shorting the CLK- pin to AGND. Win differential mode, the common mode voltage for the cis internally set to 1.2V.
3653PD_APD_B
Two-state input controlling Power Down.
PD = VA, Power Down is enabled and power dissipationreduced.
PD = AGND, Normal operation.
Two-state input controlling Output Mode.OUTSEL = VD, LVDS Output Mode.
OUTSEL = AGND, CMOS Output Mode.
23
LVDS Output Mode
24, 2526, 2728, 2932, 3334, 3539, 4041, 4243, 4447, 4849, 5051, 523738
OUTSEL
D0+,D0-D1+, D1-D2+, D2-D3+, D3-D4+, D4-D5+, D5-D6+, D6-D7+, D7-D8+, D8-D9+, D9-D10+, D10-DRDY+DRDY-
LVDS Output pairs for bits 0 through 10. A-channel and channel digital LVDS outputs are interleaved. A channelready at rising edge of DRDY and B channel is ready at falling edge of DRDY.
Data Ready Strobe. This signal is a LVDS DDR clock uscapture the output data. A-channel data is valid on the riedge of this signal and B-channel data is valid on the faledge.
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11DV200CMOS Output Mode24-29,32-35,51
Digital data output pins that make up the 11-bit conversionresult for Channel A. DA0 (pin 24) is the LSB, while DA10 (pin51) is the MSB of the output word. Output levels are CMOScompatible.
Digital data output pins that make up the 11-bit conversionresult for Channel B. DB0 (pin 39) is the LSB, while DB10 (pin52) is the MSB of the output word. Output levels are CMOScompatible.
Data Ready Strobe for channel A. This signal is used to clockthe A-Channel output data. DRDYA is a SDR clock with samefrequency as CLK rate and data is valid on the rising edges.Data Ready Strobe for channel B. This signal is used to clockthe B-Channel output data. DRDYB is a SDR clock with samefrequency as CLK rate and data is valid on the rising edges.Positive analog supply pins. These pins should be connectedto a quiet source and be bypassed to AGND with 0.1 µFcapacitors located close to the power pins.
The ground return for the analog supply.
Exposed Pad (EP) must be soldered to AGND to ensure ratedperformance.
Positive digital supply pins. These pins should be connectedto a quiet source and be bypassed to AGND with 0.1 µFcapacitors located close to the power pins.
Positive driver supply pin for the output drivers. This pin shouldbe connected to a quiet voltage source and be bypassed toDRGND with a 0.1 µF capacitor located close to the powerpin.
The ground return for the digital output driver supply. This pinshould be connected to the system digital ground.
DA0-DA10
39-44,47-50,52
DB0-DB10
37DRDYA
38
ANALOG POWER8, 16, 18, 59,
601, 4, 12, 15,22, 55, 58, EPDIGITAL POWER
21, 54
DRDYB
VA
AGND
VD
31, 45
VDR
30, 46DRGND
TABLE 1. Voltage on DF/DCS Pin and Corresponding Chip Response
Voltage on DF/DCSMin0 mV250 mV750 mV1400mV
Max200mV600 mV1250 mVVA
DF1010
DCS1001
2's complement data, duty cycle correction onOffset binary data, duty cycle correction off2's complement data, duty cycle correction offOffset binary data, duty cycle correction on
Results
Tie to AGNDLeave floating Tie to VA
Suggestions
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ADC11If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage (VA, VD VDR)Voltage on Any Pin
(Not to exceed 2.2V)
Input Current at Any Pin otherthan Supply Pins (Note 4)
Package Input Current (Note 4)Max Junction Temp (TJ)
−0.3V to 2.2V−0.3V to (VA +0.3V)
±25 mA±50 mA+150°C30°C/W
Operating TemperatureSupply Voltage (VA, VD, VDR)Clock Duty Cycle
(DCS Enabled)(DCS disabled)
VCM
−40°C ≤ TA ≤ +85°
+1.7V to +1.9
30/70 %48/52 %0.8V to 1.0
Thermal Resistance (θJA)ESD Rating (Note 6) Human Body Model2500V Machine Model250V Human Body Model750VStorage Temperature−65°C to +150°CSoldering process must comply with NationalSemiconductor's Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.(Note 7)
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHzCLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limitsapply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (Notes 8, 9)Symbol
Parameter
Conditions
Typical
Limits
(Note 10)
0.650.320.570.6013150.1402047
111.5-1.50.75-0.65±3±2.7 ±0.55 0204710.85 0.51.0
Units(Limits)
STATIC CONVERTER CHARACTERISTICS
INLDNLPGENGE
Resolution with No Missing CodesIntegral Non LinearityDifferential Non LinearityPositive Gain ErrorNegative Gain Error
−40°C ≤ TA ≤ +85°C−40°C ≤ TA ≤ +85°C
−40°C ≤ TA ≤ +85°C
Bits (min
LSB (maxLSB (min
LSB (maxLSB (min
%FS (maxppm/°Cppm/°Cppm/°C
%FS (max
TC PGEPositive Gain Error TempcoTC NGENegative Gain Error TempcoVOFF
Offset Error
Under Range Output CodeOver Range Output Code
TC VOFFOffset Error Tempco
%FS (max
REFERENCE AND ANALOG INPUT CHARACTERISTICSVRMVCMCINVRPVRN EXTVREF
Common Mode Output VoltageAnalog Input Common Mode VoltageVIN Input Capacitance (each pin toAGND) (Note 11)Internal Reference TopInternal Reference BottomInternal Reference AccuracyExternal Reference Voltage
VIN = 0.75 Vdc± 0.5 V
(VRP-VRN)
(CLK LOW)(CLK HIGH)
0.90.912.51.330.550.78
V (min)V (max)VpFpFVVV
V (Min)V (max)
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11DV200Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limitsapply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (Notes 8, 9)Symbol
Parameter
Conditions
Typical
Limits
(Note 10)
Units(Limits)(Note 2)MHzdBFSdBFSdBFS (min)dBFSdBFSdBFSdBFS (min)dBFSBitsBits (min)dBFSdBFS (min)dBFSdBFS (min)dBFSdBFS (min)dBFSdBFS
DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFSFPBW
Full Power Bandwidth (Note 16)
-1 dBFS Input, −3 dB Corner
fIN = 10 MHz, Vref = 0.75V
SNR
Signal-to-Noise Ratio (Note 13)
fIN = 10 MHz, Vref = 1.0VfIN = 70 MHz, Vref = 0.75VfIN = 70 MHz, Vref = 1.0VfIN = 10 MHz, Vref = 0.75V
SFDR
Spurious Free Dynamic Range (Note14)
fIN = 10 MHz, Vref = 1.0VfIN = 70 MHz, Vref = 0.75VfIN = 70 MHz, Vref = 1.0V
ENOBH2H3SINADIMD
Effective Number of BitsSecond Harmonic DistortionThird Harmonic Distortion
Signal-to-Noise and Distortion Ratio(Note 15)
Intermodulation Distortion (Note 16)Cross Talk (Note 16)
fIN = 10 MHzfIN = 70 MHzfIN = 10 MHzfIN = 70 MHzfIN = 10 MHzfIN = 70 MHzfIN = 10 MHzfIN = 70 MHz
fIN1 = 69 MHz AIN1 = -7 dBFSfIN2 = 70 MHz AIN2 = -7 dBFSfIN1 = 69 MHz AIN1 = -1 dBFSfIN2 = 70MHz AIN2 = -1 dBFS
90062.563.862.563.78282.48281.810.0610.06-94-94-85-8462.362.39397
61.5 71.5 9.84 -71.5 -71.5 61
Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limitsapply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)Symbol
LVDS OUTPUT MODEIAIDIDR
Analog Supply CurrentDigital Supply CurrentOutput Driver Supply CurrentPower Consumption
Power Down Power Consumption
Full Operation, Internal BiasFull Operation, External 3.3kΩ BiasFull Operation
Internal BiasExternal 3.3kΩ BiasPDA=PDB=VA
Full Operation, Internal BiasFull Operation, External 3.3kΩ BiasFull Operation
1601483734505713812431
1684183 525
mAmA (max)mA (max)mA (max)mWmW (max)mW
Parameter
Conditions
Typical(Note 10)
Limits
Units(Limits)
CMOS OUTPUT MODE (Note 12)
IAID
Analog Supply CurrentDigital Supply Current
mAmA
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(Note 10)(Limits
mWmW
ADC11
Power Consumption
Power Down Power Consumption
Internal BiasExternal 3.3kΩ BiasPDA=PDB=VA
31028060
Input/Output Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHzCLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Boldface limits apply for TMIN≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)Symbol
Parameter
Conditions
Typical(Note 10)
10.6-7.6233001.25 1001.80-20202
Limits
Units(Limits
DIGITAL INPUT CHARACTERISTICS (PD_A,PD_B)VIN(1)VIN(0)IIN(1)IIN(0)CINVOD±VODVOS±VOSRLVOHVOL+IOSC-IOSCCOUT
Logical “1” Input Voltage (Note 16)Logical “0” Input Voltage (Note 16)Logical “1” Input CurrentLogical “0” Input CurrentDigital Input CapacitanceLVDS differential output voltageOutput Differential VoltageUnbalance
Offset Voltage UnbalanceIntended Load ResistanceLogical \"1\" Output VoltageLogical \"0\" Output Voltage
Output Short Circuit Source CurrentOutput SHort Circuit Sink CurrentDigital Output Capacitance
VA = 1.9VVA = 1.7VVIN = 1.8VVIN = 0V (Note 16)
0.0.67 50 50
V (minµAµApF
V (max
LVDS OUTPUT CHARACTERISTICS (D0-D10,DRDY)
mVP-PmVVmVΩVVmAmApF
LVDS common-mode output voltage(Note 16)
VDR = 1.8V (Unloaded)VDR = 1.8V (Unloaded)VOUT = 0VVOUT = VDR
CMOS OUTPUT CHARACTERISTICS (DA0-DA10,DB0-DB10,DRDYA, DRDYB) (Note 12)
Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHzCLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Timing measurements are takeat 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)Symbol
LVDS OUTPUT MODE tCHtCLtCONVtODAtODB
Maximum Clock FrequencyMinimum Clock FrequencyClock High TimeClock Low TimeConversion Latency
DCS OnDCS OffDCS OnDCS OffDCS OnDCS Off
2.72.7
20065451.52.41.52.45/5.5(A/B)1.461.46
Parameter
Conditions
Typical(Note 10)
Limits
Units(Limits
MHz (m
MHz (m
ns (min
ns (min
Clock Cy
Output Delay of CLK to A-Channel DataRelative to rising edge of CLKOutput Delay of CLK to B-Channel DataRelative to falling edge of CLK
ns (min
ns (min
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11DV200(Note 10)
LVDS OUTPUT MODEtSUtHtADtAJtSKEW tCHtCLtCONVtODtSUtHtADtAJ
Data Output Setup TimeData Output Hold TimeAperture DelayAperture JitterData-Data Skew
Maximum Clock FrequencyMinimum Clock FrequencyClock High Time
Conversion Latency
Output Delay of CLK to DATAData Output Setup TimeData Output Hold TimeAperture DelayAperture Jitter
Relative to DRDYRelative to DRDY DCS OnDCS OffDCS OnDCS OffDCS OnDCS Off
Relative to falling edge of CLKRelative to DRDYRelative to DRDY
1.21.20.70.320 4.52.53.40.70.3
0.70.7 47017065251.762.821.762.825.53.155.811.792.69
(Limits)ns (min)ns (min)nsps rmspsMHzMHznsnsClock Cyclesns (min)ns (max)ns (min)ns (min)nsps rms
CMOS OUTPUT MODE (Note 12)
Note 1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device isguaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated underthe listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.Note 2:Units of dBFS indicates the value that would be attained with a full-scale input signal.
Note 3:All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
Note 4:When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.Note 5:The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), andcan be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device isoperated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Suchconditions should always be avoided.
Note 6:Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0Ω resistor. Charged device modelsimulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.Note 7:Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 8:The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per(Note 4). However, errors in the A/D conversion can occur if the input goes above VA or below AGND.
30087511
Note 9:With a full scale differential input of 1.5VP-P , the 11-bit LSB is 732.8µV.
Note 10:Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are notguaranteed.
Note 11:The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.Note 12:CMOS Specifications are for FCLK = 170 MHz.
Note 13:SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dBFS lower.Note 14:SFDR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 2dBFS lower.Note 15:SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.1dBFS lower.Note 16:This parameter is guaranteed by design and/or characterization and is not tested in production.
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ADC11DV200CISQE/NADC11DV200CISQX/NADC11DV200CISQ/NOOPBOPBPBADC11DV200EB/NOPB
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