数码管显示代码
library ieee;
use ieee.std_logic_11.all; entity digshow is
port(d1,d2,d3,d4,d5,d6,d7,d8:in std_logic_vector(3 downto 0); reset,clk:in std_logic;
seg:out std_logic_vector(6 downto 0); H:out std_logic;
sel:out std_logic_vector(2 downto 0)); end digshow;
architecture one of digshow is type status is(s1,s2,s3,s4,s5,s6,s7,s8); signal sta:status; signal onoff,dp:std_logic;
signal dout:std_logic_vector(3 downto 0); begin
display:process(clk,reset) begin
if(reset='0')then dout<=d1; onoff<='1'; dp<='0';
sel<=\"111\"; sta<=s1;
elsif(clk'event and clk='1')then if(sta=s1)then dout<=d1; onoff<='1'; dp<='0'; sel<=\"111\"; sta<=s2; elsif(sta=s2)then dout<=d2; onoff<='1'; dp<='1'; sel<=\"110\"; sta<=s3; elsif(sta=s3)then dout<=d3; onoff<='1'; dp<='0'; sel<=\"101\"; sta<=s4; elsif(sta=s4)then
dout<=d4; onoff<='1'; dp<='0'; sel<=\"100\"; sta<=s5; elsif(sta=s5)then dout<=d5; onoff<='0'; dp<='0'; sel<=\"011\"; sta<=s6; elsif(sta=s6)then dout<=d6; onoff<='1'; dp<='0'; sel<=\"010\"; sta<=s7; elsif(sta=s7)then dout<=d7; onoff<='1'; dp<='1'; sel<=\"001\";
sta<=s8; elsif(sta=s8)then dout<=d8; onoff<='1'; dp<='0'; sel<=\"000\"; sta<=s1; end if; end if; end process;
LED7S:process(onoff,dout,dp) begin H<=dp; if(onoff='0')then seg<=\"0000000\";
elsif(dout=\"0000\")then seg<=\"0111111\";
elsif(dout=\"0001\")then seg<=\"0000110\";
elsif(dout=\"0010\")then seg<=\"1011011\";
elsif(dout=\"0011\")then seg<=\"1001111\";
elsif(dout=\"0100\")then seg<=\"1100110\";
elsif(dout=\"0101\")then seg<=\"1101101\";
elsif(dout=\"0110\")then seg<=\"1111101\";
elsif(dout=\"0111\")then seg<=\"0000111\";
elsif(dout=\"1000\")then seg<=\"1111111\";
elsif(dout=\"1001\")then seg<=\"1101111\";
elsif(dout=\"1010\")then seg<=\"1110111\"; elsif(dout=\"1011\")then seg<=\"1111100\"; elsif(dout=\"1100\")then seg<=\"1001110\";
elsif(dout=\"1101\")then seg<=\"1011110\";
elsif(dout=\"1110\")then seg<=\"1111001\";
elsif(dout=\"1111\")then seg<=\"1110001\"; end if; end process; end one;
实验顶层设计原理图
Reset 为1正常工作时
Reset 为0的时候状态为第一个状态
