DC & Switching Characteristics
Bus Hold Specifications
Table5–29 shows the StratixII device family bus hold specifications.
Table5–29.Bus Hold Parameters
VCCIO Level
Parameter
Conditions
1.2 VMin
Low
sustaining currentHigh
sustaining currentLow
overdrive currentHigh
overdrive currentBus-hold trip point
VIN > VIL (maximum)VIN < VIH (minimum)0 V < VIN < VCCIO0 V < VIN < VCCIO
0.4522.5
1.5 VMin
25.0
1.8 VMin
30.0
2.5 VMin
50.0
3.3 VMin
70.0
Unit
MaxMaxMaxMaxMax
μA
–22.5–25.0–30.0–50.0–70.0μA
120160200300500μA
–120–160–200–300–500μA
0.950.501.000.681.070.701.700.802.00V
On-Chip Termination Specifications
Tables5–30 and 5–31 define the specification for internal termination resistance tolerance when using series or differential on-chip termination.
Table5–30.Series On-Chip Termination Specification for Top & Bottom I/O Banks(Part 1 of2)Notes(1), 2
Resistance Tolerance
Symbol
25-Ω RS3.3/2.5
Description
Internal series termination with calibration (25-Ω setting)
Conditions
VCCIO = 3.3/2.5 V
Commercial
Max
±5±30
Industrial Max
±10±30
Unit
%%
Internal series termination without VCCIO = 3.3/2.5 Vcalibration (25-Ω setting)
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Stratix II Device Handbook, Volume 1
Timing Model
Figure5–6.Measurement Setup for tzx
tZX, Tristate to Driving High DisableOEDoutOEEnable½ VCCINTDin1 MΩDin“1”Douttzh½ VCCIOtZX, Tristate to Driving Low DisableOE1 MΩOEDoutDintzl“0”½ VCCIOEnable½ VCCINTDinDoutTable5–35 specifies the input timing measurement setup.
Table5–35.Timing Measurement Methodology for Input Pins(Part 1 of2)
I/O Standard
LVTTL (5)LVCMOS (5)2.5 V (5)1.8 V (5)1.5 V (5)PCI (6)PCI-X (6)SSTL-2 Class ISSTL-2 Class IISSTL-18 Class ISSTL-18 Class II1.8-V HSTL Class I
Notes(1)–(4)
Measurement Point
VMEAS (V)
1.56751.56751.18750.8550.71251.4851.4851.16251.16250.830.830.83
Measurement ConditionsVCCIO (V)
3.1353.1352.3751.7101.4252.9702.9702.3252.3251.6601.6601.660
1.1631.1630.8300.8300.830
VREF (V)Edge Rate (ns)
3.1353.1352.3751.7101.4252.9702.9702.3252.3251.6601.6601.660
Stratix II Device Handbook, Volume 1
Timing Model
EP2S15 Clock Timing Parameters
Tables5–44 though 5–47 show the maximum clock timing parameters for EP2S15 devices.
Table5–44.EP2S15 Column Pins Regional Clock Timing ParametersParameter
tCINtCOUTtPLLCINtPLLCOUT
Minimum TimingIndustrial
1.4451.2880.104-0.053
Commercial
1.5121.3470.102
-3 SpeedGrade
2.4872.2450.336
-4 SpeedGrade
2.8482.5700.3730.095
-5 SpeedGrade
Unit
3.309 ns2.985 ns0.424 ns0.1 ns
-0.063 0.094
Table5–45.EP2S15 Column Pins Global Clock Timing ParametersParameter
tCINtCOUTtPLLCINtPLLCOUT
Minimum TimingIndustrial
Commercial
-3 Speed
Grade
2.4562.2140.3260.084
-4 SpeedGrade
2.8132.5350.3630.085
-5 SpeedGrade
3.2732.9490.4140.09
Unit
nsnsnsns
1.419 1.4871.262 1.3220.094 0.092-0.063
-0.073
Table5–46.EP2S15 Row Pins Regional Clock Timing ParametersParameter
tCINtCOUTtPLLCINtPLLCOUT
Minimum TimingIndustrial
1.2321.237-0.109-0.104
Commercial
1.2881.293-0.122-0.117
-3 Speed
Grade
2.1442.140-0.007-0.011
-4 SpeedGrade
2.4542.450-0.021-0.025
-5 SpeedGrade
Unit
2.848 ns2.843 ns-0.037 ns-0.042
ns
Stratix II Device Handbook, Volume 1
Document Revision History
Stratix II Device Handbook, Volume 1
