元器件交易网www.cecb2b.comSN74LS195AUniversal4-BitShiftRegisterThe SN74LS195A is a high speed 4-Bit Shift Register offeringtypical shift frequencies of 39 MHz. It is useful for a wide variety ofregister and counting applications. It utilizes the Schottky diodeclamped process to achieve high speeds and is fully compatible withall ON Semiconductor TTL products.http://onsemi.com•••••Typical Shift Right Frequency of 39 MHzAsynchronous Master ResetJ, K Inputs to First StageFully Synchronous Serial or Parallel Data TransfersInput Clamp Diodes Limit High Speed Termination EffectsLOWPOWERSCHOTTKYGUARANTEED OPERATING RANGESSymbolVCCTAIOHIOLParameterSupply VoltageOperating AmbientTemperature RangeOutput Current – HighOutput Current – LowMin4.750Typ5.025Max5.2570–0.48.0UnitV°CmAmA161PLASTICN SUFFIXCASE 8161SOICD SUFFIXCASE 751BORDERING INFORMATIONDeviceSN74LS195ANSN74LS195ADPackage16 Pin DIP16 PinShipping2000 Units/Box2500/Tape & Reel© Semiconductor Components Industries, LLC, 19991December, 1999 – Rev. 6Publication Order Number:SN74LS195A/D元器件交易网www.cecb2b.comSN74LS195ACONNECTION DIAGRAM DIP (TOP VIEW)VCC16Q015Q114Q213Q312Q311CP10PE9NOTE:The Flatpak version has the samepinouts (Connection Diagram) asthe Dual In-Line Package.1MR2J3K4P05P16P27P38GNDLOADING(Note a)PIN NAMESPEP0 – P3JKCPMRQ0 – Q3Q3Parallel Enable (Active LOW) InputParallel Data InputsFirst Stage J (Active HIGH) InputFirst Stage K (Active LOW) InputClock (Active HIGH Going Edge) InputMaster Reset (Active LOW) InputParallel OutputsComplementary Last Stage OutputHIGH0.5 U.L.0.5 U.L.0.5 U.L.0.5 U.L.0.5 U.L.0.5 U.L.10 U.L.10 U.L.LOW0.25 U.L.0.25 U.L.0.25 U.L.0.25 U.L.0.25 U.L.0.25 U.L.5 U.L.5 U.L.NOTES:a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.LOGIC SYMBOL945672103JKPEP0P1P2P3Q311CPMRQ0Q1Q2Q3115141312VCC = PIN 16GND = PIN 8http://onsemi.com2元器件交易网www.cecb2b.comSN74LS195ALOGIC DIAGRAMPEJ923K4P05P16P27P31MR10CPRCDQ0CPSVCC = PIN 16GND = PIN 8 = PIN NUMBERSQ015RCDCPSQ014RCDCPSQ213RCDQ3CPSQ31211Q0Q1Q2Q3Q3FUNCTIONAL DESCRIPTIONThe Logic Diagram and Truth Table indicate thefunctional characteristics of the LS195A 4-Bit ShiftRegister. The device is useful in a wide variety of shifting,counting and storage applications. It performs serial,parallel, serial to parallel, or parallel to serial data transfersat very high speeds.The LS195A has two primary modes of operation, shiftright (Q0 ³ Q1) and parallel load which are controlled by thestate of the Parallel Enable (PE) input. When the PE input isHIGH, serial data enters the first flip-flop Q0 via the J andK inputs and is shifted one bit in the direction Q0 ³ Q1 ³Q2 ³Q3 following each LOW to HIGH clock transition.The JK inputs provide the flexibility of the JK type input forspecial applications, and the simple D type input for generalapplications by tying the two pins together. When the PEinput is LOW, the LS195A appears as four common clockedD flip-flops. The data on the parallel inputs P0, P1, P2, P3 istransferred to the respective Q0, Q1, Q2, Q3 outputsfollowing the LOW to HIGH clock transition. Shift leftoperations (Q3 ³Q2) can be achieved by tying the QnOutputs to the Pn–1 inputs and holding the PE input LOW.All serial and parallel data transfers are synchronous,occurring after each LOW to HIGH clock transition. Sincethe LS195A utilizes edge-triggering, there is no restrictionon the activity of the J, K, Pn and PE inputs for logicoperation — except for the set-up and release timerequirements.A LOW on the asynchronous Master Reset (MR) inputsets all Q outputs LOW, independent of any other inputcondition.MODE SELECT — TRUTH TABLEOPERATINGMODESOPERATING MODESAsynchronous ResetShift, Set First StageShift, Reset FirstShift, Toggle First StageShift, Retain First StageParallel LoadINPUTSMRLHHHHHPEXhhhhIJXhIhIXKXhIIhXPnXXXXXpnQ0LHLq0q0p0Q1Lq0q0q0q0p1OUTPUTSQ2Lq1q1q1q1p2Q3Lq2q2q2q2p3Q3Hq2q2q2q2p3L = LOW voltage levelsH = HIGH voltage levelsX = Don’t CareI = LOW voltage level one set-up time prior to the LOW to HIGH clock transition.h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition.pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW toHIGH clock transition.http://onsemi.com3元器件交易网www.cecb2b.comSN74LS195ADC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)LimitsSymbolVIHVILVIKVOHParameterInput HIGH VoltageInput LOW VoltageInput Clamp Diode VoltageOutput HIGH Voltage2.7–0.653.50.25VOLOOutputLOWVoltageOutput LOW Voltage0.35InputHIGHCurrentInput HIGH CurrentInput LOW CurrentShort Circuit Current (Note 1)Power Supply Current–200.5200.1–0.4–10021VµAmAmAmAmA0.4Min2.00.8–1.5TypMaxUnitVVVVVTest ConditionsGuaranteed Input HIGH Voltage forAll InputsGuaranteed Input LOW Voltage forAll InputsVCC = MIN, IIN = –18 mAVCC = MIN, IOH = MAX, VIN = VIHor VIL per Truth TableIOL = 4.0 mAIOL = 8.0 mAVCC = VCC MIN,VIN = V=VIL or VorVIHper Truth TableIIHIILIOSICCVCC = MAX, VIN = 2.7 VVCC = MAX, VIN = 7.0 VVCC = MAX, VIN = 0.4 VVCC = MAXVCC = MAXNote 1: Not more than one output should be shorted at a time, nor for more than 1 second.AC CHARACTERISTICS (TA = 25°C)LimitsSymbolfMAXtPLHtPHLtPHLParameterMaximum Clock FrequencyPropagation Delay,Clock to OutputPropagation Delay,MR to OutputMin30Typ39141719222630MaxUnitMHznsnsVCC = 5.0 VCL = 15 pF 15 FTest ConditionsAC SETUP REQUIREMENTS (TA = 25°C)LimitsSymboltWtWtststrectrelthParameterCP Clock Pulse WidthMR Pulse WidthPE Setup TimeData Setup TimeRecovery TimePE Release TimeData Hold Time0Min161225152510TypMaxUnitnsnsnsnsnsnsnsVCC = 5.0 VTest Conditionshttp://onsemi.com4元器件交易网www.cecb2b.comSN74LS195ADEFINITIONS OF TERMSSETUP TIME(ts) —is defined as the minimum timerequired for the correct logic level to be present at the logicinput prior to the clock transition from LOW to HIGH inorder to be recognized and transferred to the outputs.HOLD TIME (th) — is defined as the minimum timefollowing the clock transition from LOW to HIGH that thelogic level must be maintained at the input in order to ensurecontinued recognition. A negative HOLD TIME indicatesthat the correct logic level may be released prior to the clocktransition from LOW to HIGH and still be recognized.RECOVERY TIME (trec) — is defined as the minimum timerequired between the end of the reset pulse and the clocktransition from LOW to HIGH in order to recognize andtransfer HIGH Data to the Q outputs.AC WAVEFORMSThe shaded areas indicate when the input is permitted to change for predictable output performance.PE1.3 Vts(L)th(L) = 0P0 P1 P2 P3CLOCKtPHLOUTPUT1.3 VCONDITIONS: J = PE = MR = H K = L1.3 V1.3 Vth(L) = 0tPLH1.3 VCLOCKOUTPUT*ts(L)ts(H)th(H) = 01.3V1.3 Vts(H)th(H) = 0J & KtWFigure 1. Clock to Output Delays andClock Pulse WidthFigure 3. Setup (ts) and Hold (th) Time for Serial Data(J & K) and Parallel Data (P0, P1, P2, P3) CONDITIONS: MR = H *J AND K SET–UP TIME AFFECTS Q0 ONLY MRtW1.3 V1.3 VtrecPEts(L)CLOCK1.3 VOUTPUTQn = PnQn* = Qn–1trel1.3 VLOAD PARALLEL DATA1.3 Vts(H)LOAD SERIAL DATASHIFT RIGHT1.3 Vtrel1.3 VCLOCKtPHLOUTPUT1.3 V CONDITIONS: PE = L PO = P1 = P2 = P3 = HFigure 2. Master Reset Pulse Width, Master Resetto Output Delay and Master Reset to ClockRecovery TimeCONDITIONS: MR = H *Q0 STATE WILL BE DETERMINED BY J AND K INPUTS.Figure 4. Setup (ts) and Hold (th) Time for PE Inputhttp://onsemi.com5元器件交易网www.cecb2b.comSN74LS195APACKAGE DIMENSIONSN SUFFIXPLASTIC PACKAGECASE 8–08ISSUE R–A–169NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION L TO CENTER OF LEADS WHENFORMED PARALLEL.4.DIMENSION B DOES NOT INCLUDE MOLD FLASH.5.ROUNDED CORNERS OPTIONAL.DIMABCDFGHJKLMSINCHESMILLIMETERSMINMAXMINMAX0.7400.77018.8019.550.2500.2706.356.850.1450.1753.694.440.0150.0210.390.530.0400.701.021.770.100 BSC2.54 BSC0.050 BSC1.27 BSC0.0080.0150.210.380.1100.1302.803.300.2950.3057.507.740 10 0 10 ____0.0200.0400.511.01B18FSCL–T–HKGD16 PLSEATINGPLANEJTAMM0.25 (0.010)Mhttp://onsemi.com6元器件交易网www.cecb2b.comSN74LS195AD SUFFIXPLASTIC SOIC PACKAGECASE 751B–05ISSUE J–A–NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDEMOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.MILLIMETERSINCHESMINMAXMINMAX9.8010.000.3860.3933.804.000.1500.1571.351.750.0540.0680.350.490.0140.0190.401.250.0160.0491.27 BSC0.050 BSC0.190.250.0080.0090.100.250.0040.0090 7 0 7 ____5.806.200.2290.2440.250.500.0100.019169–B–18P8 PL0.25 (0.010)MBSGFKC–T–SEATINGPLANERX 45_MD16 PLMJ0.25 (0.010)TBSASDIMABCDFGJKMPRhttp://onsemi.com7元器件交易网www.cecb2b.com
SN74LS195A
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