IEEE 1394 火线接口的设计

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FireWire Design Guide

Abstract: Guidelines for implementing FireWire (IEEE 1394) ports on both high level complex devices such as personalcomputers and simple devices such as inexpensive consumer electronics products. Includes references to normative specifi-cations as well as full reference designs that can be used as is or, with the careful consideration of the trade-offs, as a startingpoint for a more optimized design.

FireWire Design Guide

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1394 Trade Association Specifications are developed within Working Groups of the 1394 TradeAssociation, a non-profit industry association devoted to the promotion of and growth of the market for IEEE 1394-compliant products. Participants in Working Groups serve voluntarily and withoutcompensation from the Trade Association. Most participants represent member organizations of the 1394Trade Association. The specifications developed within the working groups represent a consensus of theexpertise represented by the participants.

Use of a 1394 Trade Association Specification is wholly voluntary. The existence of a 1394 TradeAssociation Specification is not meant to imply thatthere are not other ways to produce, test, measure, purchase, market or provide other goods and services related to the scope of the 1394 Trade AssociationSpecification. Furthermore, the viewpoint expressed at the time a specification is accepted and issued is subject to change brought about through developments in the state of the art and comments received fromusers of the specification. Users are cautioned to check to determine that they have the latest revision of any1394 Trade Association Specification.

Comments for revision of 1394 Trade Association Specifications are welcome from any interested party,regardless of membership affiliation with the 1394 Trade Association. Suggestions for changes indocuments should be in the form of a proposed changeof text, together with appropriate supporting comments.

Interpretations: Occasionally, questions may arise about the meaning of specifications in relationship tospecific applications. When the need for interpretations is brought to the attention of the 1394 Trade Association, the Association will initiate action to prepare appropriate responses. Comments on specifications and requests for interpretations should be addressed to:

Editor, 1394 Trade Association 315 Lincoln, Suite E Mukilteo, WA 98275 USA

1394 Trade Association Specifications are adopted by the 1394 Trade Association without regard to patents which may exist on articles, materials or processes or to other proprietary intellectual property which may exist within a specification. Adoption of a specification by the 1394 Trade Association does not assume any liability to any patent owner or any obligation whatsoever to those parties who rely on the specification documents. Readers of this document are advised to make an independent determination regarding the existence of intellectual property rights, which may be infringed by conformance to this specification.

Published by

1394 Trade Association315 Lincoln, Suite E

Mukilteo, WA 98275 USA

Printed in the United States of America

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IEEE Copyright

Portions of this specification are copied from published IEEE standards, by permission. The source documents are:

IEEE Std 1394-1995, Standard for a High Performance Serial Bus

IEEE Std 1394a-2000, Standard for a High Performance Serial Bus – Amendment 1

The IEEE copyright policy at http://standards.ieee.org/IPR/copyrightpolicy.html states, in part: Royalty Free Permission

IEEE-SA policy holds that anyone may excerpt and publish up to, but not more than, ten percent (10%) ofthe entirety of an IEEE-SA Document (excluding IEEE SIN books) on a royalty-free basis, so long as:

1) proper acknowledgment is provided;

2) the ‘heart’ of the standard is not entirely contained within the portion being excerpted. This included the use of tables, graphs, abstracts and scope statements from IEEE Documents

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Checklist

All designers of devices with FireWire ports should look for the following:

#2.1: Connectors (both plugs and sockets) shall meet the requirements laid out in the IEEE standards. ..............................7#2.2: Plugs shall have an overmold that includes strong tactile cues for orientation. ............................................................8#2.3: Sockets should be oriented so that “thumb” part of plug is on top or on the left ..........................................................9#2.4: Sockets attached to a single PHY should be close together. .......................................................................................10#2.5: FireWire 800 9-to-9 (1394b type 1) cable assemblies shields and ground shall not be shorted together. ..................10#3.1: The wiring between the connector and the PHY (TP1 to TP2 and TP3 to TP4) shall be as short as possible. ...........14#3.2: Ensure correct value for TPBIAS decoupling capacitor. ............................................................................................15#3.3: Limit FW400 common mode choke to the minimum necessary to pass EMC ...........................................................15#3.4: Implement a transient protection circuit in a power provider to protect the PHY from late VG events. ....................15#3.5: FireWire power should be current limited and filtered. ..............................................................................................16#3.6: VG must be capacitively connected to chassis ground and directly connected to PHY signal ground with minimal (pref-erably no) filtering. .............................................................................................................................................................16#3.7: The socket shield shall be directly connected to chassis ground for all unisolated ports. ..........................................16#3.8: The socket shield(s) shall be directly connected to VG at one place in the system. ...................................................17#3.9: Systems that require isolated interfaces shall use a beta-only 1394b connection. ......................................................17#3.10: FW800 ports should avoid common mode chokes. ..................................................................................................18#3.11: FW800 connector socket should internally bond the inner and outer shells. ............................................................18#3.12: FW800 TPA and TPB shields have different termination requirements than each other and for FW400 shields. ....18#3.13: Ensure signal integrity of long traces to support front panel connectors. .................................................................18#3.14: If a system has multiple PHYs and at least one of the PHYs has S800 or faster ports, then all the PHYs should be S800 or faster. ..............................................................................................................................................................................19#4.1: Ensure that Power_class is set correctly. ....................................................................................................................21#4.2: Ensure CONTENDER is deasserted ...........................................................................................................................21#4.3: Connect PCIe CLKREQ* ...........................................................................................................................................21#4.4: TI PHY core voltage is 1.95V ....................................................................................................................................22#4.5: TI PHY core voltage filtering uses 1uF caps ..............................................................................................................22#4.6: TI PHY oscillator voltage can be 1.95V ....................................................................................................................22#4.7: Ensure correct PHY/LINK pin termination when using TI PHYs in repeater mode ..................................................22#4.8: Ensure configuration and termination of unused port(s) on TI PHYs ........................................................................22#4.9: Ensure LKON/DS2 is correctly biased high or low ...................................................................................................23#4.10: Caution when TI 1394b PHY port 2 is unused or set to DS-only mode ...................................................................23#4.11: Note TI PHY max port speed is reported incorrectly for DS-mode only ports .........................................................23#4.12: Use peaking inductors on bi-lingual ports on TI PHYs ............................................................................................23#4.13: Tie PLLVDD_33 to the AVDD_3_3 power rail on TI PHYs. ..................................................................................23#4.14: Ensure that TI PHY recommendations are met ........................................................................................................23#4.15: Connect Chex OHCI_PME# to a GPIO for optimal power management .................................................................23#4.16: Ensure that Chex GRST# asserts only on link layer power cycle. ............................................................................23#4.17: Leave Chex GPIO’s as no-connects .........................................................................................................................24#4.18: Bring Chex CYCLEOUT to a test point ...................................................................................................................24#4.19: Connect VDD_33_AUX to 3.3V ..............................................................................................................................24#4.20: Ensure TI Link devices implementation requirements are met ................................................................................24#4.21: Ensure power is provided during sleep mode for TI Link devices. ..........................................................................24#4.22: Ensure that G_RST* timing requirement is met .......................................................................................................24#4.23: G_RST* is asynchronous .........................................................................................................................................24#4.24: Ensure VAUX_DETECT is pulled high on FW3 .................................................................................................25#4.25: Ensure FW3 power reset is stuffed consistently with regulation of 1.0V supply .................................................25#4.26: Ensure LSI integrated PHY/Link devices implementation requirements are met .....................................................25#4.27: Ensure power is provided during sleep mode for LSI integrated PHY/Link devices. ..............................................25#4.28: Ensure PME is uniquely identifiable to software for LSI FW323 v129. ..................................................................25#4.29: Internal or external pull-downs required on PHY/Link interface .............................................................................27#4.30: Special termination may be needed if PHY/Link propogation delay is > 1 ns .........................................................274

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FireWire Design Guide

#5.1: All components and traces between the protection diode and the connector need to support 33V or higher. .............29#5.2: PHY operation should not be affected by power provider current limiter trips ..........................................................29#5.3: System operation of power providers should not be affected by power consumer inrush or shorts. ...........................29#5.4: Power Class 4 power providers should implement appropriate CSRs. .......................................................................30#5.5: Bus powered portable devices and peripherals should declare the appropriate power class. ......................................30#5.6: Power consumers should implement the power management CSRs. ..........................................................................30#5.7: Ensure that CPS is correctly connected ......................................................................................................................32#6.1: OHCI link must reliably meet real-time requirements under anticipated load. ...........................................................40

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Contents

2. Mechanical.........................................................................................................................................................................7

2.1 Connectors............................................................................................................................................................72.2 End-to-end connections......................................................................................................................................103. Port design.......................................................................................................................................................................14

3.1 Interfaces............................................................................................................................................................143.2 Connector/PHY wiring.......................................................................................................................................14

3.2.1 Termination..............................................................................................................................................173.2.2 Front panel (“remote”) connector wiring guide.......................................................................................183.3 Testing Advice....................................................................................................................................................194. System design..................................................................................................................................................................21

4.1 PHY selection.....................................................................................................................................................214.2 PHY configuration recommendations.................................................................................................................21

4.2.1 General.....................................................................................................................................................214.3 Link layer recommendations..............................................................................................................................21

4.3.1 PCIe recommendations............................................................................................................................214.4 Specific device recommendations.......................................................................................................................22

4.4.1 TI TSB81BA3..........................................................................................................................................224.4.2 TI XIO2213 (Cheetah Express, aka Chex)...............................................................................................234.4.3 Texas Instruments TSB82AA2 1394b link device...................................................................................244.4.4 LSI FW3..............................................................................................................................................254.4.5 LSI FW323..............................................................................................................................................254.5 PHY/Link interface.............................................................................................................................................27

4.5.1 Additional requirements...........................................................................................................................274.5.2 Layout guide............................................................................................................................................285. Cable power.....................................................................................................................................................................29

5.1 Introduction........................................................................................................................................................295.2 FireWire power checklistrecommendations........................................................................................................295.3 FireWire device guidelines.................................................................................................................................305.4 Example Circuits................................................................................................................................................31

5.4.1 Desktop alternate power provider............................................................................................................335.4.2 Desktop primary power provider with backup power pass-through.........................................................345.4.3 Portable computer....................................................................................................................................355.4.4 Peripherals or mobile devices..................................................................................................................365.5 Notes...................................................................................................................................................................37

5.5.1 Power Classes (for reference)..................................................................................................................375.5.2 Note on diode protection..........................................................................................................................375.5.3 Use of Power Down and Cable Not Active..............................................................................................385.5.4 Trade Association Cable Power Distribution Specification - proposed variations...................................396. Link selection...................................................................................................................................................................40

6.1 OHCI requirements.............................................................................................................................................406.2 Target devices.....................................................................................................................................................40

6.2.1 Asynch peripherals...................................................................................................................................406.2.2 Media/consumer electronics.....................................................................................................................406

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7. Firmware/higher layers.....................................................................................................................................................41

7.1 Basic node operation...........................................................................................................................................41

7.1.1 Bus initialization......................................................................................................................................417.1.2 Configuration ROM.................................................................................................................................417.1.3 Isochronous Resource Manager................................................................................................................417.1.4 Bus Manager............................................................................................................................................427.1.5 Required performance..............................................................................................................................427.1.6 Interoperability issues..............................................................................................................................427.2 Mass storage devices..........................................................................................................................................42

7.2.1 SBP profile...............................................................................................................................................427.2.2 AV profile.................................................................................................................................................427.3 Imaging devices..................................................................................................................................................42

7.3.1 Printers.....................................................................................................................................................427.3.2 Scanners...................................................................................................................................................427.3.3 Still image cameras..................................................................................................................................427.3.4 Machine vision cameras...........................................................................................................................427.4 Consumer electronics..........................................................................................................................................43

7.4.1 Tape recorders..........................................................................................................................................437.4.2 Televisions...............................................................................................................................................437.4.3 Set top boxes............................................................................................................................................437.4.4 Disks........................................................................................................................................................437.4.5 Audio equipment......................................................................................................................................437.5 Professional........................................................................................................................................................43

7.5.1 Audio.......................................................................................................................................................447.5.2 Video........................................................................................................................................................447.6 Automobile.........................................................................................................................................................447.7 Industrial/Instrumentation...................................................................................................................................448.1 Layout recommendations for S800 1394b TSB81BA3 Physical Layer:.............................................................519. Firewire Design Guide – Robust Port Design...................................................................................................................57

12.1 Conformance terminology................................................................................................................................7512.2 Technical glossary.............................................................................................................................................75

Figures

Figure2-1— Plug overmold ..................................................................................................................................................8Figure2-2— Socket orientation (as viewed from outside of bulkhead) ................................................................................9Figure2-3— Legacy socket orientation (as viewed from front of product) ..........................................................................9Figure2-4— 1394b type 1 cable assembly and schematic (Beta plug to Beta plug) ...........................................................11Figure2-5— 1394b type 2 cable assembly and schematic (Legacy 6 circuit plug to Bilingual plug) .................................12Figure2-6— 1934b type 3 cable assembly and schematic (Legacy 4-circuit plug to Bilingual plug) .................................13Figure3-1— Measurement points (half connection is shown) ............................................................................................14Figure5-1— A multiport Power Provider class 1/2/3 node .................................................................................................32Figure5-2— A multiport Power Provider class 4 node .......................................................................................................33Figure5-3— A multiport Power Provider class 1/2/3 node, operating as Class 4 when power is not available ..................34Figure5-4— A multiport Alternate Power Provider class 4 node .......................................................................................35Figure5-5— A single port bus-powered (class 4) node ......................................................................................................36Figure5-6— A multiport bus-powered (class 4) node ........................................................................................................36Figure5-7— Diodes to provide power management domains .............................................................................................38Figure8-1— Example FW800 OHCI Controller .................................................................................................................46Figure10-1— Example extendible two port power management IC ...................................................................................72Figure10-2— Using multiple two port power management ICs .........................................................................................73

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Tables

Table2-1— Insertion and removal force (tentative) .............................................................................................................7Table2-2— 1394b type 1 (Beta to beta) end-to-end connections .......................................................................................11Table2-3— Legacy 6 circuit to 1394b Bilingual end-to-end connections ..........................................................................12Table2-4— Legacy 4 circuit to 1394b Bilingual end-to-end connections ..........................................................................13Table3-1— 1394b receiver characteristics .........................................................................................................................14Table4-1— Phantom cycles caused by MI cycle reflection ................................................................................................27Table5-1— Power class ......................................................................................................................................................37

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2.2.1Connectors

Item #2.1:Connectors (both plugs and sockets) shall meet the requirements laid out in the IEEE stan-dards.

Sockets must strongly resist “backwards” insertion

This means that the “narrow” part of the socket shall not have a split unless there is a mechanical reinforcement that pre-vents the narrow end from spreading when a plug is inserted backwards. It further means that the mechanical tolerencesspecified in [2], [3], and [4] must be met. In particular, the socket should meet the following insertion force requirements:

Table2-1—Insertion and removal force (tentative)

Condition

6-pin plug correctly aligned inserted into 6-pin socket

9-pin plug correctly aligned inserted into 9-pin socket6-pin plug correctly aligned removed from 6-pin socket

9-pin plug correctly aligned removed into 9-pin socket6-pin plug reverse aligned inserted into 6-pin

socket

9-pin plug reverse aligned inserted into 9-pin

socket

Insertion/removal

force

< 1 N

Comment

measured using a plug that is at the maximum dimensions allowed by 1394, and

maximum value before any of the VG, VP, or TPx contacts mate, and

must have a noticeable “click” or “snap” when fully insertedmeasured using a plug that is at the minimum dimensions allowed by 1394, and

minimum value before any of the VG, VP, or TPx contacts separate, and

must have a noticeable “click” or “snap” when removedmeasured using a plug that is at the minimum dimensions allowed by 1394, and

minimum force before any of the VG, VP, or TPx contacts mate, and

socket must be noticeably damaged by reverse insertion (allows diagnosis of improper use)

> 1 N

> 10 N

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Item #2.2:Plugs shall have an overmold that includes strong tactile cues for orientation.

flat surfaceR0.70 max (2x)246135R2.5 min (2x)Recommendedround surfaceNOTRecommendedRecommendedNOTRecommendedBeta/bilingual 9-pin

Legacy 6-pin

Figure2-1—Plug overmold

Overmold cues are to provide hints for where the user should put the thumb.a)b)

Flat surface corresponds with “flat” surface on narrow axis

Round surface corresponds with “angled” surface on narrow axis

This will assist in preventing attempted backwards connection (particularly if the connector placement rules describedbelow are followed).

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FireWire Design Guide

Item #2.3:Sockets should be oriented so that “thumb” part of plug is on top or on the left

Sockets should have a standard orentation to aid the “blind” insertion of the plug. Since the plug overmold has features toencourage the placement of the thumb in a particular spot, and most people prefer to put their thumb on top of a plug asthey insert it, the socket itself should be oriented so that the “thumb” feature is on top as viewed looking at the bulkheadfrom the outside. And since most people are right handed,. the alternate positioning should have the “thumb” feature onthe left. Figures 2-2 and 2-3 illustrate the concept.

Horizontal reference(Not PCB mounting)LegacyRecommendedRecommendedNotRecommendedNotRecommendedBeta/BilingualFigure2-2—Socket orientation (as viewed from outside of bulkhead)

... or as viewed from the front of a hypothetical product:

Rear portsLeft portsRight portsFront portsFigure2-3—Legacy socket orientation (as viewed from front of product)

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Item #2.4:Sockets attached to a single PHY should be close together.

Connectors, PHY, protection and termination components for a single port are best seen as a lumped circuit. The min. risetime for 1394a is 0.5 ns which implies 1 GHz waveforms, while the min. rise time for 1394b is 0.080 ns, over 6 GHz!If both front and back panel sockets are desired, then there are two choices:a)b)

separate PHYs for front and back (two PHYs and one Link), or

a very carefully designed “remote” socket where the entire path from the PHY termination network (seeclause3.2.2) to the socket is within 1394 requirements (110 ± 6 Ω differential mode and 33 ± 6 Ω common mode,more details in [2]). Note that this is quite unlikely to be successful for a S800 or faster port.

2.2End-to-end connections

Item #2.5:FireWire 800 9-to-9 (1394b type 1) cable assemblies shields and ground shall not be shorted together.

Since the new 1394b connections are unfamiliar with designers, the end-to-end connections for the various 1394b cablesare described in figure2-4, table2-2, figure2-5, table2-3, figure2-6 and table2-4.

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FireWire Design Guide

NOTE—The legacy interface cables (type 2 9-to-6 and type 1 9-to-4) do short some of the shields and ground together. It is importantthat this be done correctly for each cable type.

plug 1plug 243521677216NOTE—Cable as defined in 1394b. Connectors are viewed as looking at the front plug face.

Figure2-4—1394b type 1 cable assembly and schematic (Beta plug to Beta plug)

Table2-2—1394b type 1 (Beta to beta) end-to-end connections

SignalChassis GroundChassis Ground, HF to Logic GroundTPA

PCB pad1311

Socket/plug nameChassis Ground

Socket/plug connectionOuter shell

Cable(no connect)Outer shield

Socket/plug connectionOuter shellInner shell

Socket/plug nameChassis Ground

PCB pad12

Signal

Chassis GroundChassis Ground, HF to Logic GroundTPBLogic GroundTPB*Logic Ground(no connect)FW PWRTPA

High frequency to Logic GroundTPA*

Chassis Ground, HF to Logic GroundChassis Ground

43Cable Shield Inner shellGroundTPATPA(R)TPA*VGSCVPTPBTPB(R)TPB*

453678291

5Cable Shield 10GroundTPBTPB(R)TPB*VGSCVPTPATPA(R)TPA*

291678453

Signal pair #1 red

Signal pair #1 shieldSignal pair #1 greenPower pair #1 white(no connect)Power pair #1 blackSignal pair #2 blue

Signal pair #2 shieldSignal pair #2 orangeOuter shield

291678453Inner shell

High frequency to 5Logic GroundTPA*Logic Ground(no connect)FW PWRTPBLogic GroundTPB*

Chassis Ground, HF to Logic GroundChassis Ground

367829110

Cable Shield Inner shellGroundChassis Ground

Outer shell

Cable Shield 11GroundChassis Ground

12(no connect)Outer shell

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plug 2

4356plug 1

7246

NOTE—Cable (reference) IEEE Std 1394-1995. Connectors are viewed as looking at the front plug face.

Figure2-5—1394b type 2 cable assembly and schematic (Legacy 6 circuit plug to Bilingual plug)

Table2-3—Legacy 6 circuit to 1394b Bilingual end-to-end connections

Signal

PCB pad

Socket/plug name

Socket/plug connection

Cable(no connect)

Chassis Ground, HF to Logic GroundTPALogic GroundTPA*Logic Ground

6252

Cable Shield Plug shellGroundTPAVGTPA*VG

6252

Outer shield

Socket/plug connectionOuter shellInner shell

Socket/plug nameChassis Ground

PCB pad12

SignalChassis GroundChassis Ground, HF to Logic GroundTPBLogic GroundTPB*Logic Ground(no connect)

Cable Shield 10GroundTPBTPB(R)TPB*VGSCVPTPATPA(R)TPA*

29167

21Signal pair #1 red2Signal pair #1 shieldSignal pair #1 greenPower pair #1 white(no connect)Power pair #1 blackSignal pair #2 shieldSignal pair #2 orangeOuter shield

91678

FW PWRTPBLogic GroundTPB*

Chassis Ground, HF to Logic Ground

1423

VPTPBVGTPB*

1423

8FWPWR453

TPA

High frequency to

Logic GroundTPA*

Chassis Ground, HF to Logic GroundChassis Ground

Signal pair #2 blue4

53Inner shell

Cable Shield Plug shellGroundCable Shield 11GroundChassis Ground

(no connect)Outer shell

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FireWire Design Guide

plug 2

4372156plug 1

4321

NOTE—Cable (reference) IEEE Std 1394a-2000. Connectors are viewed as looking at the front plug face.

Figure2-6—1934b type 3 cable assembly and schematic (Legacy 4-circuit plug to Bilingual plug)

Table2-4—Legacy 4 circuit to 1394b Bilingual end-to-end connections

Signal

PCB pad

Socket/plug name

Socket/plug connection

Cable(no connect)

(no connect)

Outer shield

Socket/plug connectionOuter shellInner shell

Socket/plug nameChassis Ground

PCB pad12

SignalChassis GroundChassis Ground, HF to logic GroundTPBLogic GroundTPB*Logic Ground(no connect)FW PWRTPA

High frequency to Logic GroundTPA*

Chassis Ground, HF to logic GroundChassis Ground

Cable Shield 10GroundTPBTPB(R)TPB*VGSCVPTPATPA(R)TPA*

291678453

TPALogic GroundTPA*

4TPAShell

4Plug shell3

Signal pair #1 redSignal pair #1 shieldSignal pair #1 green(no connect)(no connect)(no connect)

29167853Inner shell

3TPA*

TPBLogic GroundTPB*

2TPBShell

2Plug shell1

(no connect)

Signal pair #2 blue4Signal pair #2 shieldSignal pair #2 orangeOuter shield

1TPB*

Cable Shield 11GroundChassis Ground

(no connect)Outer shell

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FireWire Design Guide

3.There are a number of good 1394 port design application notes. The TI notes on EMI [11] and layout [12] as well as theLSI design guide for the FW323 [13] are particularly good. Every designer of FireWire systems should be familiar withthese documents. Much of the following is derived from those application notes.

3.1Interfaces

All interface specifications apply at the points of entry and exit from the equipment. The interface specifications may be“valid” at other places. These points are identified as points TP2 and TP3 as shown in Figure3-1. The specificationsassume that all measurements are made after a mated connector pair, relative to the source or destination. TP1 and TP4are reference points for use by implementors to specify vendor components. In particular, PHY IC specs apply at TP1 fortransmit and TP4 for receive.

The reference points for all connections are those points TP2 and TP3 at the transitions between the cabinet and the cableshield. If sections of transmission line exist within the cabinet shield, they are considered to be part of the associatedtransmit or receive network, and not part of the cable plant.

TP1T+T-PHY

TP2TP3TP4TRANSMITNETWORK

RECEIVENETWORK

R+R-PHY

Figure3-1—Measurement points (half connection is shown)

NOTE—Do not confuse “TPn” where “n” is the number one through four with the “TPx” where “x” is “A” or “B”. TPn refers to a testpoint and TPx refers to a twisted pair signal.

3.2Connector/PHY wiring

Item #3.1:The wiring between the connector and the PHY (TP1 to TP2 and TP3 to TP4) shall be as short as possible.

The TPA and TPB pairs carry very high speed signals, and so must be imlemented using good design practices for highspeed circuits and interfaces to external devices. The impedance requirements for the connector/PHY wiring shall meet1394b requirements (included below for reference).

Table3-1—1394b receiver characteristics

Parameter

Input impedance test conditions:TDR rise timeException windowaInput impedance @ TP3:Through connectionbAt terminationc

110 ± 20110 ± 10

ΩΩ

100700

50700

psps

S400β

S800β

S1600β

Units

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Table3-1—1394b receiver characteristics

Parameter

Differential skew

Common mode input impedance

S400β5%

S800β5%> 550

S1600β5%

UnitsUIΩ

Within the Exception-window no single impedance excursion shall exceed the Through-connection impedance tolerance for a period of twice the TDR rise time specification.b.

Through connection impedance describes the impedance tolerance through a mated connector. This tolerance is greater than the termination or cable impedance due to limits in the technology of the connectors.

c. The input impedance at TP3, for the termination, shall be recorded 4.0ns following the electrical reference plane determined by the receptacle on the receiver bulkhead

NOTE—1394 bilingual and FW400 ports have transmitter and receiver on both the TPA and TPB signals, so the receiver inputimpedance spec applies for both pairs.

3.2.0.1Termination

The TPA pair has the required 110 ¾ differential termination as close as possible to the PHY, with the center point of thetermination attached to the PHY’s bias output for that port and capacitively to signal ground (each port on the PHY shallhave an independent bias output – this is required to prevent a short on one port from causing all the other ports to notoperate).

Item #3.2:Ensure correct value for TPBIAS decoupling capacitor.

The PHY’s tpbias output should be decoupled with a 0.33 μF capacitor to ground, unless the PHY is a TI PHY. TI PHYsneed a 1.0 μF to ground, so as to guarantee a minimum ripple on the tpbias voltage under a worst-case speed-signalingscenario, which is necessary in the TI design to maintain stability of the tpbias driver. The lower value is needed whenusing non-TI PHYs in order to meet the 1394a timing specification for tpbias assertion and deassertion.

3.2.0.2TP EMC/EMI protection

Item #3.3:Limit FW400 common mode choke to the minimum necessary to pass EMC

FW400 ports may need a high speed common mode choke, particularly if the PHY-to-connector layout is long or runsnear possible signal sources. Individual components must be used for each signal pair to limit crosstalk between TPA andTPB. The choke must allow the lower fequency common mode speed signals to get through (while removing high fre-quency common mode signals). In general, this means that the common mode impendence must be less than 165 Ohms at100 MHz, and the differential impedence less than 15 ohm at 100 MHz.

Products should use the minimum choke necessary to pass EMC. The design should anticipate evaluation of EMC com-pliance with several values (for example, the Murata DLP11SN range starts at 67 Ohms, with variants at 90 Ohms, 120Ohms and 160 Ohms), and with not using a common mode choke at all. This can be achieved by designing the layout toallow a common mode choke or a 0 Ohm resistor.

3.2.0.3Transient protection

Item #3.4:Implement a transient protection circuit in a power provider to protect the PHY from late VG events.

Power providers should have a diode clamping network between the PHY and the socket to provide two functions:a)

ESD protection so that the high voltage is drained to the chassis, and

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“Late VG” protection (so called because the power provided on VP can appear on the TPx signals if the VGconnection takes place after the VP and at least one of the TPx connections is completed). Note that this lastfunction requires that chassis ground and signal ground have a low resistance connection somewhere (see Item#3.8:below).

The high side clamp diodes use a 3.6V nominal zener diode prebiased with a 3.3V source via a 330 Ohm current limintingresistor (other sources may be used with an appropriate resistor value). This provides a nominal 2.4V, worst case 2.1VESD and late-VG rail to the BAV99 diodes. In turn, allowing for a 0.6V drop through the diodes, this will permitFireWire signaling at up to 2.7V without compromising signal integrity. A late-VG event on the signal pairs will bedrained back to ground via the Zener diode. Late VG events can be of a long duration, and they represent a return pathfor the VP supply, so the current must be directed back to VG. Despite its rating, the recommended Zener has been mea-sured as being capable of sustaining a current of 300mA, up to 2W, keeping the voltage level on the signal pins to lessthan 5.5V, which the PHY is also able to tolerate. Under more stress, either the PHY fails or the Zener. The Zener tendsto fail short, which results in the TPA/TPB pairs being held to GND and preventing FireWire operation. Lower voltageZeners, which have been used in some designs, tend to fail before the PHY, increasing the system return rate unnecessar-ily.

ESD events are of a short duration and will be drained from digital ground to chassis ground and from there to earthground. It is acceptable to use signal ground instead of chassis ground for the transient protection network since signalground is capacitively connected to chassis ground at the connector. This can only be done if there is no ferrite on the VGpath (see Item #3.6:below). The galvanic connection between chassis ground and signal ground must be low impedanceat the frequencies not handled by the capacitive connection at the connector.

If a common mode choke is used, then the transient supression network should be placed on the PHY side of the choke.The advantage of having the diodes on the PHY side is that the common mode choke can be placed closer to the connec-tor for better EMI performance.

Late-VG does not occur on self powered devices.Transient protection iodes must have a very low capacitance (less than0.5 pF).

3.2.0.4Power and ground interface (VG/VP)

Item #3.5:FireWire power should be current limited and filtered.

VP should be current limited 1.5 A and EMI filtered to minimize system noise getting out to peripherals. Current limitcan be done using a polyfuse, although their slow trip speed requires careful thought put towards the effect of momentaryexcess current draw. A choke between 50 ohm and 1000 ohm (at 100 MHz) is acceptable in the path for EMI filtering andshould be located close to the sockets. A 0.010µf capacitor should connect to chassis ground immediately next to thesocket.

Item #3.6:VG must be capacitively connected to chassis ground and directly connected to PHY signal ground with minimal (preferably no) filtering.

VG should AC connect to chassis ground immediately next to the socket using a 0.010µf capacitor. There must not be asignificant impedance in the path between VG and the PHY signal ground since VG is the return path for the commonmode speed signalling sent out on TPB and received on TPA. If a filter is implemented, it should be designed to pass thespeed signal (100-120ns pulse of about 20ma on VG). Usually this means any ferrite in the VG path must be 50 ohm orless at 100 MHz.

3.2.0.5Shield interface

Item #3.7:The socket shield shall be directly connected to chassis ground for all unisolated ports.

There should be a chassis ground plane underneath the socket for this purpose. The galvanic isolation options defined in1394a and 1394-1995 should no longer be used.16

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Item #3.8:The socket shield(s) shall be directly connected to VG at one place in the system.

This is usually achieved by connecting chassis ground to VG at one place in the system. Whether any further connectionis required, and if so the optimal placing of this is a matter for system design when considering EMC compliance andnoise immunity. In general, a DC connection between the socket shield and VG should not be made at the connector,though an allowance for this for experimental purposes may be made by using a 0 Ohm no-stuff. In addition, all uniso-lated systems must have the connector shield AC coupled (frequency characteristics TBD) to VG near the connector (seeItem #3.6:above). The DC connection between shield and VG is needed for the return path of VP when it sneaks throughTPx in the case of a “late VG” connection,

Item #3.9:Systems that require isolated interfaces shall use a beta-only 1394b connection.

The 1394b beta-only connection is a much more robust interface for isolated ports. All use of the 1394a and 1394-1995“floating PHY” implementation with a galvanically isolated PHY-Link interface is discouraged.

3.2.0.6Layout guidelines

The TPA/TPB pairs carry both high speed differential and lower speed common mode signals (with VG as the commonmode return). Skew between the pairs is important. Some general rules:a)b)c)d)e)f)g)

maximize routing symmetry

maximize via transitioning symmetryno 90 degree corners

a maximum of two vias in the path for FW400 ports and one via in the path for FW800 ports, and all signals inthe port TPA+, TPA-, TPB+ and TPB- must have the same number of viasdifferential intra-pair skew less than 10ps for the differential trace on the PCBinter-pair skew less than 25ps on the PCB for ports supporting FW400

minimize distance between connector and PHY (system-dependent, but 25 mm is a good choice for the maximumfor a 1394a port and 12mm for a bi-lingual port as these are roughly the distance traveled in the minimum risetime for the appropriate signals).

termination as near PHY as possible (< 10 mm, closer is better)minimize the stub length for termination resistors and diodes

provide a semi-isolated ground plane for the 1394 port signals (connect with system ground plane only at thePHY)

no other signals should be routed across or near the TPA/TPB pairs, particularly not clock lines or any signals orground/power planes associated with switching power supplies.

the digital ground plane should extend to the point where the digital signals are connected to the connector. Achassis ground plane should be provided under the connector, but should not extend into the board area used forthe digital signal routes.

read and learn about high speed circuit design!

h)i)j)k)l)

3.2.1Termination

Same as FW400, see clause3.2.0.1. Layout is critical.

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3.2.1.1TP EMC/EMI protection

Item #3.10:FW800 ports should avoid common mode chokes.

FW800 PHYs are extremely sensitive to signal distortion caused by the extra impedence and capacitance added bycommon-mode chokes. Fortunately, FW800 PHYs also generate an exceeding clean differential signal, so a choke is notneeded to eliminate residual common-mode currents. This places requirements on the designer to be exceedingly carefulthat the TPA/B pairs do not add common mode noise (very close in length, isolated from noise sources, etc.). The 1394bconnector also provides better emissions control when transmitting 1394a signaling.

Item #3.11:FW800 connector socket should internally bond the inner and outer shells.

The need for a common mode choke may be avoided by ensuring that the connector socket internally bonds the inner andouter shells together. This is appropriate for all designs that do not use galvanic PHY/Link isolation. (Note that the innershell on the connector plug is connected to the outer shield of the cable.)

If previous experience with similar designs indicates that a common mode choke may be required, then this should beanticipated by designing the layout to allow a common mode choke or a 0 Ohm resistor. If a common mode choke provesto be necessary, then one designed for either DVI or S800 1394b is required. A suitable device is the TDK ACM2012H-900-2P.

3.2.1.2Shield interface

Item #3.12:FW800 TPA and TPB shields have different termination requirements than each other and for FW400 shields.

The individual pair shields have their own connections in the 9-pin socket. The shield for TPA must connect to digitalground via a high value resistor (1 MΩ or greater) in parallel with a 0.1 μF capacitor and to the chassis ground via a 0.001μF capacitor. The shield for TPB must connect directly to digital ground and to chassis ground via a 0.001 μF capacitor.Same as FW400 for VP and VG, see clause3.2.0.5.

3.2.2Front panel (“remote”) connector wiring guide.

Item #3.13:Ensure signal integrity of long traces to support front panel connectors.

When a front panel connection is required to be supported by a PHY primarily intended for real panel connections, thenthe traces on the circuit board must be effectively shielded from the noise produced by the rest of the system and thelengths very carefully controlled (see the layout guide above.). In addition, if the signal pairs travel farther than a risetime equivalent (0.5ns or about 25mm), the 110±6 Ω impedance must be maintained for the entire length. Note that addi-tional design, layout, and test time may be necessary to ensure that the extra EMC/EMI, signal degradation, and imped-ance matching requirements are satisfied.

Front panel connections using a single PHY that primarily serves back panel connections are discouraged for several rea-sons:a)b)c)

It is much easier to get a reliable system if the connector-to-PHY distance is minimized.

The cable length budget calculated for cable assemblies is always done assuming there is no significant lengthadder inside the system (TP1-TP2 and TP3-TP4). This can affect total signal attenuation budgets.

A front panel connection is only useful for a system that is always right in front of the user. A desktop typesystem could provide this, but a tower system is typically under a desk. A better solution for a tower systemwould be to include a FireWire hub in the package and allow the user to place the hub wherever it is most useful.

When front panel access is required then the following possible solutions should also be considered:

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Compromise on the position of the connector. Perhaps move all the FireWire sockets to the side (like old iMacs)or take advantage of the size of the system to make backside connectors easily accessible (like the new iMacs).b)Consider adding a second PHY to the design that can be placed directly next to the front panel connector. The

routing of the TPA/B pairs between the back and front PHYs is less critical since it will be short and terminatedat both ends. In addition, there are no special consideration for external cable design since almost all of theattenuation budget can be used by the cable assembly. One important note:

Item #3.14:If a system has multiple PHYs and at least one of the PHYs has S800 or faster ports, then all the PHYs should be S800 or faster.

This is because a system that ships with mixed S800 (or faster) and FW400 PHYs will always be a “hybrid” bus and willnot be able to run in the more efficient “pure beta” mode. Even if a PHY only has FW400 external connectors, it shouldbe an S800 (or faster) PHY with an S800β (or faster) connection to the other system PHY(s). The user of such a systemwill then always have the advantages of pure beta bus as long as nothing is connected to the FW400 port(s).

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4.4.1PHY selection

All PHYs should be reevaluated with the vendors at each design cycle. In particular, the following checklist should beused:a)

Determine the actual parameters of the PHY (measured at TP1 and TP4 in figure3-1). They should be better thanthe 1394 specifications, since the 1394 specifications are measured at the connector (TP2 and TP3 in figure3-1),and your design will add extra circuit elements between the PHY and the connector pins which will degrade thesignal.

Protection features outlined previously are best done if incorporated in the PHY itself. Encourage PHY vendors todo this.

The PHY/Link interface (and any other bidirectional or output pins that are potentially connected to CMOSinputs) should be pulled down by a high resistance path. This is to avoid excess current draw by the CMOSreceiver on the other end of the signal when the PHY is powered down, or when the interface is disabled by thePD signal.more TBD.

b)c)

4.2PHY configuration recommendations4.2.1General

Item #4.1:Ensure that Power_class is set correctly.Item #4.2:Ensure CONTENDER is deasserted

It is important that the node does not contend to be Isochronous Resource Manager until and unless software is ready. ThePHY’s contender pin must always be deasserted.

4.3Link layer recommendations4.3.1PCIe recommendations

Item #4.3:Connect PCIe CLKREQ*

CLKREQ* should be connected to the enable of the clock chip associated with the PCIe REFCLK+/-. The clock chip inturn should be programmed either to ignore the enable (and always provide the clock) or programmed to accept theactive-low request depending on system power management. Typically this signal is open drain and requires a 10K pull-up.

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4.4Specific device recommendations4.4.1TI TSB81BA3

See clause5. for details on power class determination and implementation.

Item #4.4:TI PHY core voltage is 1.95V

The nominal 1.8V power rails DVDD-1.8 and PLLVDD-1.8 require 1.95V +-0.1V. If a filtering resistor is used, then a fil-tering resistor of 1 Ohm is recommended. Due to the voltage drop through the filtering resistor, the 1.95V LDO shouldtarget a voltage of 1.96V.

Item #4.5:TI PHY core voltage filtering uses 1uF caps

TI recommends one 1uF capacitor on each DVDD_CORE power terminal places as close to the device as possible(directly underneath if possible) to provide filtering.

Item #4.6:TI PHY oscillator voltage can be 1.95V

Although the XI input is documented as a 1.8V input, TI confirm that it is acceptable to run this as a 1.95V input, pow-ered from the same rail as the core voltage.

Item #4.7:Ensure correct PHY/LINK pin termination when using TI PHYs in repeater mode

If a TI PHY is used in repeater mode, i.e. a mode in which it does not have an attached link layer (for example, on a frontpanel), then the PHY link interface pins should be terminated as follows:-Unconnected: PINT, CTRL0, CTRL1, D0:D7, PCLK (1394b PHY), SCLK (1394a PHY)Pulled low through a 1K resistor: LPS

Pulled directly to GND: LREQ, LCLK (1394b PHY)Pulled high through a 1K resistor: BMODE (1394b PHY)

Item #4.8:Ensure configuration and termination of unused port(s) on TI PHYs

An unused port 0 or port 1 should be configured into DS-only mode by tying DS0 or DS1 respectively to VDD via 1KOhm resistor. This prevents toning and saves power.

An unused port 2 should be configured into DS-only mode by tying LKON/DS2 to VDD via 470 Ohm resistor. This pre-vents toning and saves power.

The TPA+ and TPA- pins should be left as no-connects (tying them to GND can cause a false connection to be detected).The TPB+ and TPB- should be tied together and tied directly to GND. The TPBIAS terminal should be left as a no-con-nect.

Note: If a design allows for a connector as an option (i.e. in product variants with the same PCB layout), then TPBIAScan be connected to GND via the normal 1uF filtering capacitor (this would normally be a stuff option) and the TPB+ andTPB- pins connected via the normal 55 Ohms to a common mode point and thence via a 5K Ohms to GND (these wouldnormally be stuff options, with 0 Ohm stuff options to connect TPB+/- directly to GND when the port is not used).

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Item #4.9:Ensure LKON/DS2 is correctly biased high or low

If port 2 is to operate in DS mode or is unused then LKON/DS2 should be tied high via a 470 Ohm resistor and a series1K Ohm resistor be used to connect to the link’s PHY_LINKON pin. This is required to ensure correct biasing of the con-figuration setting if the link chip is unpowered (the internal ESD protection circuitry in the link acts as a pull-down), andcorrect signaling of LinkOn to the link. If port 2 is to operate in bi-lingual mode then LKON/DS2 should be tied low viaa 1K Ohm resistor and directly connected to the link’s PHY_LINKON pin (no series termination).

Note that this updates earlier recommendations to use other values for pull-up/down resistors or series termination resis-tors.

Item #4.10:Caution when TI 1394b PHY port 2 is unused or set to DS-only mode

Port 2 on a TI 1394b PHY is set to DS only mode by tying LKON/DS2 high via a 470 Ohm resistor. During power reset(normally this occurs only when power is first applied to the PHY) this will cause the link layer to see LKON high. Inturn this may cause a software interrupt. This requires the link layer to be active before the PHY layer completes reset,and is an unlikely scenario, but is noted for reference in the case of initialization issues in new system designs.

Item #4.11:Note TI PHY max port speed is reported incorrectly for DS-mode only ports

If a port is forced to DS-only mode then the TI PHY correctly limits connections to S400 (DS), However, register 10 inthe PHY register map for the port reports max_port_speed as 3 (S800) rather than 7 (DS-only).Test and production software needs to work around this. This issue is fixed in Rev D.

Item #4.12:Use peaking inductors on bi-lingual ports on TI PHYs

Peaking inductors are recommended for TI PHY ports that are connected to bilingual connectors to open the transmit eyewhen operating in Beta mode. Peaking inductors are strongly recommended for signal integrity with PHYs included inMCM packages, and are suggested for all PHYs. A value of 18 nH is recommended, and the inductors should be in serieswith the 55 Ohm termination resistors (between the resistor and the common mode bias / termination point).

Item #4.13:Tie PLLVDD_33 to the AVDD_3_3 power rail on TI PHYs.

They are tied together inside the device.

4.4.2TI XIO2213 (Cheetah Express, aka Chex)

Item #4.14:Ensure that TI PHY recommendations are met

The TI XIO2213 incorporates a TI PHY. All the recommendations for the TI PHY apply to Chex.

Item #4.15:Connect Chex OHCI_PME# to a GPIO for optimal power management

By connecting this signal to a GPIO (for example, on a Southbsridge), a software interrupt can be given on a PHY event(such as a new connection) even if Chex and its PCIe connection are in a low power mode with clocks off. Software canthen restore full power operation and take appropriate action. This signal has an open drain driver and requires a 10Kpull-up.

Item #4.16:Ensure that Chex GRST# asserts only on link layer power cycle.

This is a platform reset that should be applied only when the link layer power rails are power cycled (and, in particular,only shortly before the time when EFI will initialize the device). In particular, it should not be applied over a sleep/wakecycle.

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Item #4.17:Leave Chex GPIO’s as no-connects

This applies to GPIO0-GPIO7.

Item #4.18:Bring Chex CYCLEOUT to a test point

CYCLEOUT is a valuable signal for scope triggering when carrying out diagnostic investigations. Bring to a convenienttest point for scope triggering with a 47K pull-down.

Item #4.19:Connect VDD_33_AUX to 3.3V

VAUX isn't supported from D3cold and the AUX power detect bit is hardwired to 0. However, connecting VDD_33_AUXto 3.3V provides minimum power consumption.

4.4.3Texas Instruments TSB82AA2 1394b link device4.4.3.1Texas Instruments Link implementation requirements

Item #4.20:Ensure TI Link devices implementation requirements are met

Use or otherwise of the internal 1.8V regulator makes negligable difference to overall power consumption. If it is notused, then 1.8V should be provided on the REG18 terminal and the REG_EN* terminal tied high via a 1K Ohm resistor.An external PCI/OHCI configuration ROM is not required, and the SCL and SDA pins should be tied to ground via 220Ohm resistors. PCI_RST* should be connected directly to PCI_RST_L, it does not need to be gated by the SMC.

4.4.3.2Sleep mode power required

Item #4.21:Ensure power is provided during sleep mode for TI Link devices.

The TI link family of devices do not preserve the GUID setting if power is removed from the device. It is important forsoftware that the GUID is set once on system power reset, and then never needs to be updated, otherwise a security holeis opened up. Consequently it is necessary to preserve power to the device during sleep, even for single port designs.Equally G_RST* must be used once when AC power is first supplied and then never again.

Item #4.22:Ensure that G_RST* timing requirement is met

The timing requirements on G_RST* require that the signal be asserted (held low) for at least 2ms and that the rise timebe less than 4.3ms. In general, this prevents the use of a RC circuit to the power rail. It should be connected to a PowerOK or similar signal that will have a duration of at least 2ms..

Item #4.23:G_RST* is asynchronous

There is a datasheet error with respect to the timing requirements of G_RST* and the PCI clock. G_RST* is an asynchro-nous signal, and, in contrast to the requirements specified in the datasheet, it may be deasserted before the PCI clock isprovided.

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4.4.4LSI FW3

Item #4.24:Ensure VAUX_DETECT is pulled high on FW3

The package pin VAUX_DETECT must be pulled high to allow sticky reset to be a separated from non-sticky reset. Oth-erwise PERSTN will reset the sticky domain as well which will result in, for example, the GUID being lost.VAUX_DETECT is pulled down by default at the pad, and must be pulled high externally with a 10K (??) pull-up.

Item #4.25:Ensure FW3 power reset is stuffed consistently with regulation of 1.0V supply

The FW3 has an internal Power Up Reset (PUR) cell to insure logic is properly initialized and the crystal oscillatorcircuit has stabilized on power up. The internal PUR cell has no voltage ramp requirement. The PUR cell monitors theVDD10 ramp and generates an internal reset signal that is used to reset its internal flops and deactivate its internal coun-ter until VDD10 reaches about 40 – 70% of its peak value (rising threshold). The output of the PUR stays low duringthis time and continues in the low state for the PUR period. The output switches to logic high once that time is reachedand the internal counter is also disabled at that point. The front end has a built-in hysteresis and a filter capacitor toreject VDD10 noise once VDD10 is up. The cell also detects the falling ramp of VDD10. When VDD10 falls beyond acertain level (designated by falling threshold), the output of the PUR cell goes LOW.

If the internal regulator controller of the FW3 (and associated external circuitry) is used to generate the 1V powersupply, no circuitry is necessary on the FW-RESET_N input. It has an internal pull-up and can be left unconnected.However, if the VDD10 and VDD33 power supplies are controlled independently, the customer needs to insure that theVDD33 supply has reached its required voltage level (3.3V +/- 10%) before the VDD10 power supply has reached 40%of it's required voltage level to guarantee sufficient time for the crystal oscillator to stabilize. Alternatively, the active lowFW_RESET_N input can be asserted until the 3.3V power supply has reached its required voltage level. This will extendthe length of the power-up reset in insure that the crystal oscillator is stable.

4.4.5LSI FW323

4.4.5.1LSI integrated PHY/Link implementation requirements

Item #4.26:Ensure LSI integrated PHY/Link devices implementation requirements are met

The CNA and LPS outputs are not used and should be not connected. An external OHCI configuration ROM is notrequired, and the ROM_CLK and ROM_AD pins should be tied to ground. Configuration pins that are asserted (typicallyCARDBUSN and none or more of PC0, PC1 and PC2) should be tied to VDD via a 10K Ohm resistor. PCI_RST* shouldbe connected directly to PCI_RST_L, it does not need to be gated by the SMC.

4.4.5.2Sleep mode power required

Item #4.27:Ensure power is provided during sleep mode for LSI integrated PHY/Link devices.

The LSI FW323 family of devices do not preserve the GUID setting if power is removed from the device. It is importantfor software that the GUID is set once on system power reset, and then never needs to be updated, otherwise a securityhole is opened up. Consequently it is necessary to preserve power to the device during sleep, even for single port designs.Equally RESETN must be used once when AC power is first supplied and then never again.

Item #4.28:Ensure PME is uniquely identifiable to software for LSI FW323 v129.

As LinkOn is not pinned out on this device, the only way when the device is in low power mode that software finds outthat there is a new connection, or disconnection, or similar significant event, is via PCI PME. It is important that softwareis able to distinguish this PME interrupt from other PME interrupts, so that it does not needlessly poll the device on irrel-evant PME interrupts (this involved waking the PCI clock domain parts of the device, initializing it, reading registers, dis-covering that there has been no change, and putting the device back to sleep again). This can be accomplished by

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connecting the PME interrupt to a dedicated GPIO, or ensuring that the PCI bus is not shared by any other devices and isbridged in such a way that the FW323’s PME interrupt is readily distinguishable from PME interrupts from othertdevices. A dedicated GPIO is the preferred solution, so that the driver can handle a range of system devices in a similarway.

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4.5PHY/Link interface

The PHY/Link interface shall follow the specifications in 1394a Annex J1 or 1394b Clause 17. If the 1394b PIL/FOPinterface is used, then 1394b Clause 18 shall apply.

Series termination (typically 22 ohms) may be beneficial in some designs, but has also been observed to aggravate prob-lems with reflections (see Item #4.30:below).

4.5.1Additional requirements

Item #4.29:Internal or external pull-downs required on PHY/Link interface

All signals between the Link, PHY and other system components shall be pulled down to signal ground with a high resis-tance. This pull down must be active even when the Link, PHY (or other system component) is powered down. If this isnot done, signals could drift into the CMOS switching region resulting in excess power consumption or unreliable opera-tion. The suggested method is for both the PHY and Link to include internal pull-downs; if this is not done, then externalpull-downs are needed.

Item #4.30:Special termination may be needed if PHY/Link propogation delay is > 1 ns

If the PHY/Link interface propogation time is greater than about 1 ns then reflections at the clock cycle when a devicehands back the interface to its peer can be seen by this device at the next clock. In particular, the device can mis-interpreteither or both of CTRL[1:0] and some or all of DATA[7:0]. This effect has been seen on systems where the PHY/Linkinterface is > 1.4ns. The effect has also been seen to be worse when 22 ohm series termination is used at the peer device.In addition, when the link hands back the interface to the PHY, the effect also depends on the delay from PClk receivedat the link to when CTRL and DATA are clocked out at the link interface. The link times when it drives these signals withrespect to LClk, but after handing back the interface to the PHY, the link samples the same signals using PClk.

The effect is most likely to occur when the link hands back the interface to the PHY after transmitting aMORE_INFORMATION cycle. The misread can result in the link seeing a phantom RECEIVE cycle, GRANT cycle orSTATUS cycle. A phantom RECEIVE cycle will normally be benign (a 1 cycle runt packet). A phantom GRANT cyclecould cause the link to transmit another packet while the PHY has control of the interface - causing the PHY to miss someor all of the packet. A phantom STATUS cycle can cause the link to misbehave simply because there may be more thanone of D[0:7] set (only one bit is set in a valid status cycle), but in particular cause unfairness (delayed asynchronouspackets) or isochronous phase confusion (link delays one cycle before transmitting an isochronous packet). The followingtable summarizes the possible phantom cycles as seen by the link.

Table4-1—Phantom cycles caused by MI cycle reflection

D lines[0][1][2][3][4][5][6][7]Transmitted MORE_INFO cycle (CTL = 11)Format (Beta = 1)PH_NEXT_EVEN/PH_NEXT_ODD/PH_CYCLE_START_REQPH_ISOCH_REQ_EVEN/PH_CURRENT/PH_NEXT_ODD

PH_ISOCH_REQ_ODD/PH_CURRENT/PH_NEXT_ODD

EOSSpeed = S400/S800Speed = S200/S800-Sampled Status cycle (CTL = 01)

PH_BUS_RESET_START

PH_ARB_RESET_ODDPH_ARB_RESET_EVENPH_ISOCH_ODDPH_ISOCH_EVENPH_SUBACTION_GAP--Sampled Grant cycle (CTL = 11)

Grant Format (Beta = 1)Grant Type = Async/CS/Immediate

Grant Type = Isoch/CS/ImmediateGrant Type = Async/Immediate

-Grant Speed = S400/S800Grant Speed = S200/S800-Sampled RX cycle (CTL = 10)

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4.5.2Layout guide

Care must be taken to avoid crosstalk between PCI signals and FireWire high speed signals and/or ground-bounce fromPCI signaling. Ensure that there is sufficient grounding for the PCI interface, and keep separate from FireWire groundingif possible.

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5.5.1Introduction

A major benefit of FireWire is the ability to power (and recharge, for that matter) devices from the bus. When designinga device, it is important to consider whether and when the device will be a power consumer (power itself from the bus,possibly charging its batteries), a power provider (provide power to other devices on the bus) and/or a power repeater(repeat power received on one port to other ports on the device), and whether it might provide more than one of thesefunctions in different power states.

A significant concern on a bus is to ensure that there is sufficient power available for all the power consumers. Everydevice is allowed to power its PHY from the bus at all times, and indeed consume up to 3W. A device may not consumemore power than this until permitted by a power manager. The “LinkOn” PHY command packet is sent from the powermanager to a power consumer when the power manager determines that sufficient power is available. A limited amountof status is provided on bus reset to enable a power manager to evaluate power needs and availability.Currently, power managers are not implemented!

The main reference for power distribution is the 1394 Trade Association Document “Power Specification Part 1: CablePower Distribution” TA 1999001-1 (October 5th 1999) and the main reference for power management is the 1394 TradeAssociation Document “Power Specification Part 3: Power Distribution Management” TA1999001-3 (January 15, 2000).However, there are significant differences in the recommendations in this document. These differences are summarizedbelow.

NOTE—a device normally incorporates a single PHY, and appears on the bus as one node. If a device incorporates more than one PHY,then these rules apply separately to each PHY (each node).

5.2FireWire power checklistrecommendations

Item #5.1:All components and traces between the protection diode and the connector need to support 33V or higher.

External power providers may provide power at up to 30V.

Item #5.2:PHY operation should not be affected by power provider current limiter trips

Designs should be such that the PHY will continue operating if the regulatory current limiter trips. Note that the lack ofprovision of power will often cause bus resets, and the status of “PS” (Cable Power Status) will change as the current lim-iter repeatedly trips and resets.

Item #5.3:System operation of power providers should not be affected by power consumer inrush or shorts.

When a FireWire device is connected to a power provider, or suddenly consumer extra power (for example a disk drivestarting to spin up) ,the inrush current can cause a dip in the voltage on the power rail used to provide FireWire power.This in turn can affect operation of other parts of the system dependent on the same rail. Some devices have been seen notto respect the inrush limits, and a similar but worse problem can occur if a faulty shorted FireWire device is attached.Protection against this is normally implemented within the system power architecture. In addition, it may be helpful toinclude current-limiting series resistors in the FireWire power rail. The port fuse is basically a short for a few secondsafter a shorted FW device is attached, and the current limit resistor limits current so that the AC/DC can source currentlong enough to blow the fuse. Note that these resistors are special, untrimmed surge resistors, so system designers have tobe sure to get the right kind of resistors. The need for such resistors, and the appropriate value to use, willl vary accordingto system design.

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Without such resistors, a short between VP and VG will trip the power adapter and possibly bring the system down. How-ever, the initial value chosen for the resistors may well result in the resistors frying before the polyfuse blows. The finalsolution in this case may be to use relatively low value resistors (0.025 Ohm 1W) with a 0.5A polyfuse. Note that therating of the polyfuse gives the maximum current at which the fuse is guaranteed not to open. Polyfuses typically willsustain a load of up to 2x their nominal rating, and the resistors need to be able to sustain this load.

Item #5.4:Power Class 4 power providers should implement appropriate CSRs.

Any node declaring itself as Power Class 4 and which provides power (i.e. is an Alternate Power Provider) should imple-ment the Power Management CSRs that indicate its power providing capability. (PowerClass 4 really means “go read theCSRs to find out what I do”). These are defined in [6].

Item #5.5:Bus powered portable devices and peripherals should declare the appropriate power class.

When a device is powered from the bus, it must declare itself as power class 4, 6 or 7 as appropriate (less than 3W total,7W total or 10W total consumption from the bus). In power classes 6 or 7, it must support LinkOn, and respect the rulesfor consuming no more than 3W until LinkOn is received. A node which requires more than 10W power, for example tocharge its batteries, should either (a) declare itself as Class 4, use less than 3W for PHY, link and management purposes,or (b) use Class 6, use less than 7W for PHY, link and management purposes and support LinkOn. In both cases it shouldthen use Power Management CSRs to declare its requirement for up to 45W and to allow its consumption to be controlledby a Power Manager.

See the examples in clause5.4.4.

Item #5.6:Power consumers should implement the power management CSRs.

These are defined in [6].

5.3FireWire device guidelines

PA1)When a device is connected to mains power, it provides power to the bus either

a)b)

as a Primary Power Provider, providing 20W at greater than or equal to 20V (recommended 24-26V) declaringitself as power class 1, or

as an Alternate Power provider, providing 8W at 12-15 V, declaring itself as power class 4 (for multiple portdevices) or power class 0 (for single port devices), and powers its PHY from the bus if possible.

PA2)When a device is connected to mains power, it provides power to the bus as an Alternate Power provider, providing8-16W at 12-15V, declaring itself as power class 4 (for multiple port devices) or power class 0 (for single port devices).

Higher power provision (between 20W and 45W) is left to external hubs.

The device provides power to the bus when connected to mains power even if in “sleep” or “off”.

PA3)When a single port device is powered from battery power, it either

a)b)(portable device) when running provides power to the bus as an Alternate Power Provider (power class 0),providing 8W at a protected battery rail (normally between 9.25 V and 15 V), or(mobile device, never connected to mains power) never provides power to the bus.

PA4)When a multiple port device is powered from battery power, it either

(portable device) when running provides power to the bus as an Alternate Power Provider (power class 4),providing 8W at a protected battery rail (normally between 9.25 V and 15 V) and when in sleep or off powers itsPHY from the bus if possible, or

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b)(mobile device, never connected to mains power) never provides power to the bus.

PA5)When a device is powered from the bus, it must declare itself as power class 4, 6 or 7 as appropriate (less than 3Wtotal, 7W total or 10W total consumption). In power classes 6 or 7, it must support LinkOn, and respect the rules for con-suming no more than 3W until LinkOn is received. A node which requires more than 10W power, for example to chargeits batteries, should either (a) declare itself as Class 4, use less than 3W for PHY, link and management purposes, or (b)use Class 6, use less than 7W for PHY, link and management purposes and support LinkOn. In both cases it should thenuse Power Management CSRs to declare its requirement for up to 45W and to allow its consumption to be controlled bya Power Manager.

PA6)(Future requirement) A node which may consume more than 3W from the bus should include Power ManagementSoftware. This is to avoid being dependent on non-existent or inadequate power managers! Without power managementthere is a possibility of a bad user experience.

PA7)At any time that a node changes power class, then it advertises this with a short (arbitrated) bus reset. Care needs tobe taken with power provision sequencing (provide power before changing power class to advertise its availability,remove power only after changing power class advertising its lack of availability).

PA8)The protection circuitry for Primary Power Providers shall include per-port diode protection to (a) prevent consump-tion of bus-supplied voltages and (b) alleviate the problem of being overridden by a higher voltage power provider, andshall include per-port resettable fuses to limit the current drawn through any port. The protection circuitry for all multiple-port power providers shall include per-port resettable fuses to limit the current drawn through any port. Each port shallsupport but shall not exceed 1.5A. Note that this protection is needed to protect against current summing from one ormore ports and/or the internal power provider to the power provided on another port. In addition, current limiters shall beincluded for all power providers so that the provision of internal power is not affected by a short on any VP wire. See ref-erence circuits below.

PA9)Any node declaring itself as Power Class 4 and which provides power (i.e. is an Alternate Power Provider) shouldimplement the CSRs which indicate its power providing capability. (PowerClass 4 really means “go read the CSRs to findout what I do”).

PA10)Designs should be such that the PHY will continue operating if the regulatory current limiter trips. Note that thelack of provision of power will often cause bus resets, and the status of “PS” (Cable Power Status) will change as the cur-rent limiter repeatedly trips and resets.

PA11)A power brick is detected by the presence of power but the absence of a connection on a port. A node may con-sume as much power as it can extract from a power brick.

PA12)Any multiport device without per-port power protection diodes (typically a Power Class 4 node) must be designedat least to power the PHY from the bus in cases where no local power is available (unplugged, etc.). In no case can power“flow through” a device without data also being repeated. System may be allowed to violate this rule when not connectedto mains power where this is considered not a normal mode of operation.

5.4Example Circuits

This clause shows example circuits (including power provision, PHY Vdd from bus power, and all protection circuits) fora variety of applications. Note that these circuits are only shown as functional examples, they are not exact implementa-tions. In particular, the use of so many diodes in a high current system is discouraged because of the power dissipationdue to forward current losses. Switches with a polarity detect might be a better choice.

Annex10. briefly describes a hypothetical integrated circuit that could be used to implement all the following examples.

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Item #5.7:Ensure that CPS is correctly connected

Multiple port systems that may be powered from cable power must take the CPS tap at the point at which the VP connec-tions to the various ports are OR’d together in order to ensure that the presence of cable power is reported correctly. Sys-tems that may in some situations not power the PHY when cable power is present should take this input from the powerprovision side of the isolating diode in order to prevent pump-up current entering the PHY when it is not powered(although any such current, necessarily via the high value series resistor, will be very small).Desktop, server or hub primary power provider

A normal stationary device or a hub may be a primary power provider. This allows power to be much more easily man-aged (see above), and up to 45W output per port, if desired. Power domain isolation is provided by means of the per-portdiodes Power is provided to the PHY and to the ports as log as main power is available (while the device is plugged in),even if in “sleep”..

25V cable power sourcetrickle power source

system-dependent

current limit1.5A current

limit

1394 Conn.

1.5A current

limit

V Reg for PHY only needed if trickle power voltage is not compatible with

PHY

VPVG

V Reg

1.5A current

limit

1394 Conn.

VPVG

PHY

per-port limits only needed if the system-dependent limit is greater than 1.5A

1394 Conn.

VPVG

PHY ground

Figure5-1—A multiport Power Provider class 1/2/3 node

1.5A current limiters are only required on each port if the device can provide more than 1.5A since 1394 requires that nomore than 1.5A be consumed via any port (1394/1394a speed signaling fails if more than 1.5A is consumed via a port)..

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5.4.1Desktop alternate power provider

Another way to build a desktop sytsem is as an “alternate power provider” which does not have per-port diode isolation.This device will provide power when plugged in, even if in “sleep” or “off”. Since it does not prevent power from flow-ing from one port to another, it must also guarantee that the PHY repeats data whenever there is bus power. This meansthat the PHY must get its power from the bus as shown below in figure5-2 .

12-18V cable power sourcetrickle power source

system-dependent

current limit1.5A current

limit

1394 Conn.

1.5A current

limit

VPVG

V Reg

1.5A current

limit

1394 Conn.

VPVG

PHY

per-port limits always needed since power can be “added” through any port

1394 Conn.

VPVG

PHY ground

Figure5-2—A multiport Power Provider class 4 node

When local power is provided, then power is provided to the PHY and to the three ports. There is no power domain iso-lation: power flows freely between the ports.

When local power is not provided the PHY operates using bus power.

1.5A (min.) current limiters are required on each port because the example device has two or more ports. They provide ameasure of regulatory power protection (without them, a faulty device on one port could consume excessive power frompower providers upstream on the other port(s) and/or the system). The current limiters must allow at least 1.5A, but also1394 requires that no more than 1.5A be consumed via any port (1394/1394a speed signaling fails if more than 1.5A isconsumed via a port).

A node with this design must ensure that port power pass through is not set for a port in suspend.

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5.4.2Desktop primary power provider with backup power pass-through

It is also possible to combine the two previous designs, allowing a node to be a primary power provider whenever mainpower is available, yet passing power and data through when main power is turned off.

25V cable power sourcetrickle power source

system-dependent

current limit1.5A current

limit

1394 Conn.

1.5A current

limit

VPVG

V Reg

1.5A current

limit

1394 Conn.

VPVG

PHY

switches open when providing power

1394 Conn.

VPVG

PHY groundlocal power off

Figure5-3—A multiport Power Provider class 1/2/3 node, operating as Class 4 when power is not available

This device provides power to 1394 when plugged in, even if in “sleep”.

When local power is provided, then the three switches are held open. Power is provided to the PHY and to the three ports.Power domain isolation is provided by means of the three per-port diodes.

When local power is not provided, then the three switches are held closed. Power is repeated between the ports and thePHY operates using bus power. Note that operation should be phased so that any power consumers connected via any ofthe ports do not see an interruption in power supply when power is applied or withdrawn locally. The switches are openedafter local power becomes available (but before the bus reset declaring power class 1, 2 or 3), and are closed before localpower is withdrawn (but after the bus reset declaring power class 4).

1.5A (min.) current limiters are required on each port because the device has three or more ports. They provide a measureof regulatory power protection (without them, a faulty device on one port could consume excessive power from powerproviders upstream on the other two ports). The current limiters must allow at least 1.5A, but also 1394 requires that nomore than 1.5A be consumed via any port (1394/1394a speed signaling fails if more than 1.5A is consumed via a port).A node with this design must ensure that port power pass through is not set for a port in suspend.

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5.4.3Portable computer

Portable computers will normally be Alternate Power Providers, which are intended for applications with only a limitedamount of power..

mains power

source

batterypowernot sleep

system-dependent

current limit1.5A current

limit

1394 Conn.

1.5A current

limit

VPVG

1394 Conn.

V Reg

1.5A current

limit

VPVG

1394 Conn.

PHY

VPVG

PHY ground

Figure5-4—A multiport Alternate Power Provider class 4 node

This device provides bus power whenever the device is plugged into the wall, or the device is operating on battery andnot sleeping. The PHY is powered from the bus when bus power voltage exceeds system-provided cable power voltage,otherwise it is powered from the local supply.

1.5A (min.) current limiters are required on each port if a device has two or more ports. They provide a measure of regu-latory power protection (without them, a faulty device on one port could consume excessive power from power providersupstream on the other port(s) and the internal supply). The current limiters must allow at least 1.5A, but also 1394requires that no more than 1.5A be consumed via any port (1394/1394a speed signaling fails if more than 1.5A is con-sumed via a port).

A system-dependent current limit is provided to protect the local supply against excessive demand by external devicesand for regulatory purposes.

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5.4.4Peripherals or mobile devices

A single port mobile device may provide power to its PHY using the main supply, if appropriate. This is acceptablebecause the device does not repeat the FireWire signal

to internal bus-powered functions

V Reg(opt. batt. & charger)

PHY

PHY ground

system power switch1394 Conn.

VPVG

Figure5-5—A single port bus-powered (class 4) node

A multiport mobile device is required to repeat the FireWire signal, so its PHY should always be powered whenever thereis bus power available. It can optionally use power from the main device power supply, if the device itself is always pow-ered when there is bus power.

A mobile bus power device with 3 or more ports must have 1.5A current limiters on each port. They provide a measureof regulatory power protection (without them, a faulty device on one port could consume excessive power from powerproviders upstream on the other two ports). The current limiters must allow at least 1.5A, but also 1394 requires that nomore than 1.5A be consumed via any port (1394/1394a speed signaling fails if more than 1.5A is consumed via a port).

to internal bus-powered functions

V Reg(opt. batt. & charger)

system power switch1.5A current

limit

1394 Conn.

1.5A current

limit

VPVG

separate PHY VReg not needed if device always bus powered

V Reg

1.5A current

limit

1394 Conn.

VPVG

PHY

per-port limits needed for 3 or more ports since power can be “added” through any port

1394 Conn.

VPVG

PHY ground

Figure5-6—A multiport bus-powered (class 4) node

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A node with this design cannot use 1394 port-suspend.

5.5Notes

5.5.1Power Classes (for reference)

Power consumption and source characteristics are shown in table5-1:

Table5-1—Power class

Power class(binary)00020012010201121002101211021112

Power class01234567

Description

Node does not need power and does not repeat power.

Node is self-powered and provides a minimum of 15 W to the bus.Node is self-powered and provides a minimum of 30 W to the bus.Node is self-powered and provides a minimum of 45 W to the bus.

Node may be powered from the bus and is using up to 3 W. No additional power is needed to enable the linka.Reserved for future standardization.

Node is powered from the bus and is using up to 3 W. An additional 3 W is needed to enable the linka.Node is powered from the bus and is using up to 3 W. An additional 7 W is needed to enable the linka.

5.5.2Note on diode protection.

A power provider node uses a diode to protect its internal circuitry from drawing power from the bus when another powerproviding node is providing power at a higher voltage than the local node. This can be achieved using a single diode onthe power supply.

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However, a primary power provider is required to implement a per port diode. This assists in the creation of separatepower domains, each powered by a single power provider. The result is to reduce the number of scenarios in which theconnection of another power provider can disrupt existing devices (see example below in figure5-7), to reduce thenumber of scenarios in which an individual cable may be overloaded, and to assist power management software do its job.

Running system

Provides up to 30W at 20VVpConsumes 10W

Add another power provider

Provides up to 30W at 20VVpConsumes 10W

Provides 15W at 30V

VpConsumes 10WConsumes 10W

The new power provider overrides the original power provider due to providing power at a higher voltage, but does not provide enough power for the power consumers. It will either droop (allowing power sharing,

which is OK) or will crowbar (possibly repeatedly). The configuration is difficult for a Power Manager to control.Add another power provider with per-port diode isolation

Provides up to 30W at 20V

Provides 15W at 30V

VpVpConsumes 10WConsumes 10W

Per-port diode isolation allows the original power provider to continue to provide power to the

power consumers - power domain isolation (each power provider powers a separate power domain)

Figure5-7—Diodes to provide power management domains

Per-port diode protection is required for Primary Power Providers.

5.5.3Use of Power Down and Cable Not Active

Some devices provide pins on the PHY to report no activity on the cable (CNA - Cable Not Active) and/or to allow PowerDown (PD). These may be used in 1394a systems to provide power savings on the PHY.More TBD

Some devices may use Suspend or Standby if there is no connection/active port to save power.

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5.5.4Trade Association Cable Power Distribution Specification - proposed variations

Multi-port power consumers are permitted. They repeat power.

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6.All host-level devices (CPUs) shall use an Open Host Controller Interface design for the Link layer, devices for embeddedapplications in computer peripherals or consumer electronics have more freedom.

6.1OHCI requirements

a)b)

The OHCI for FW400 applications shall follow the OHCI 1.1 specification. See [9]The OHCI for FW800 applications shall follow the OHCI 1.2 specification. See [10]

Item #6.1:OHCI link must reliably meet real-time requirements under anticipated load.

OHCI design must be matched with the encompassing system so that FireWire real-time requirements can be reliably metunder anticipated load, such as Final Cut Pro; the OHCI FIFO depth and isochronous transmit packet workahead must besufficient to cope with worst-case host memory contention, or stated inversely, host memory performance to FireWiremust be fast and frequent enough to satisfy the OHCI's workahead and FIFO depth limitations. Stated either way, onemust consider DMA descriptor fetch and status overhead in addition to actual payload bandwidth.

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7.7.0.0.1IRM not root

If an Isochronous Resource Manager discovers that it is not root (and therefore not cyclemaster), then it has some respon-sibilities to ensure that the bus is configured both correctly and optimally.

Given that there is no incumbent bus manager, it should proceed immediately to reading the Bus_Info_Block of the root. If the root is cycle master capable then it should immediately set its force root flag and clear the flag on all other nodes(by sending out a PHY configuration packet with the R bit set and the phy_ID of the root), and set the cmstr bit in theSTATE_CLEAR register of the root node. This is because the current root may have become root “by chance” with noforce_root bit set in any node at the time of the bus reset. It is necessary to make sure that the next time there is a busreset for any reason, the root stays root (unless the IRM or the BM is explicitly deciding that someone else should beroot). Sending out the PHY configuration packet does this. It is the IRM’s responsibility in the absence of a bus manager,to do this. No one else will.

If the root is not cycle master capable, then the IRM have to hunt round for a node that is (The IRM itself is probably agood candidate!) and make that node root (by setting its force_root flag and invoking a new arbitrated bus reset). It isimportant to get an active cyclemaster going within 125 usec of a bus reset – so it is not practicable to wait for the elec-tion of a new bus manager, for example.

The IRM is allowed to detect the presence of root as cyclemaster by the detection of cycle start packets, should the rootstart sending these quickly. This may save the necessaity of reading the Bus_Info_Block, but the IRM must not wait longto detect the absence of cycle start packets!

7.0.0.21394a IRM-capable node

If the node is 1394a IRM-capable (i.e. implements the BROADCAST_CHANNEL register, with channel 31 allocated asthe default broadcast channel)? If so, then it should check whether the current IRM (when not itself) has this capability.If it does not, then it should make itself root and IRM.There are four tests – use one or more of them:-a)b)c)d)

receipt of a write request addressed to your BROADCAST_CHANNEL register that sets the valid bit to 1 (musthave come from a 1394a IRM)

successful completion of a read request addressed to the IRM’s B_C register with the most significant bit set inthe response

successful read of the IRM’s bus information block that shows the generation field to be non-zero

analysis of self_ID’s shows that the IRM has not changed, and previously was known to be 13954a compliant

See 8.4.2.3 in 1394a (page 169).

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8.NOTE—As of 10/14/2009, this document includes the latest schematic drawings provided by Texas Instruments.

This FW800 PCI reference design has been contributed by Texas Instruments. The power circuitry and PCI connector por-tions of the schematic are provided only to show a complete design and may not be applicable to all PCI applications. Formore schematic and layout information, see appropriate TI application note.

NOTE—This design needs minor updates. See the main text for correct components, etc.

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Figure8-1—Example FW800 OHCI Controller

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Notes on Example FW800 OHCI Controller (figure8-1.)

For cost reduction, input signal terminals may be tied directly to GND if required to set their state. However for more conservative (better) ESD performance, signal pins that need to be set to a ground state should be pulled to ground through a resistor valued from 220 Ohms to 1.2 Kohms (general guideline for values).

2)The oscillator in the reference design has a 3.3V output. The PHY XI pin requires a 1.8V input

signal. Therefore there is a voltage divider on the output of the oscillator to shift the oscillator 3.3Voutput to a 1.8V level for the input to the PHY. It is also possible to use a 1.8V oscillator and avoidthe use of a voltage divider. The oscillator circuits must be laid out to minimize noise and inducedjitter. The oscillator used must be an extremely low jitter oscillator. Using a separate Vcc powerplane for the oscillator can help minimize jitter and noise.

3)LCLK is a 98.304MHz input to the PHY that should be series terminated to reduce standing waves at its

source (the 1394b link layer).

4)CPS is a connection from the PHY, which has internal signals of 500MHz, to the cable, which is a large

antenna. The 390K resistor should help prevent EMI, but if required a ferrite may be placed in series with theCPS signal to reduce the chance of PHY signals unintentionally getting on the 1394b cable.

5)LPS determines if the PHY-link interface is active, a pulldown is included so that even if the PHY is

powered, but the link is not powered, that the LPS pin will be in the correct state.

6)Pin 26 is not used, but will have a 98.304MHz signal present on it. To help prevent EMI the customer may

terminate this signal with an approximately 10K Ohm resistor to ground.

7)To pull up a signal to the power rail, an approximately 1 K Ohm pullup should be used. Pins should not be

tied directly to a power rail.

8)It is recommended that pins 2, 32, 33, 73, 66, 67, and 68 (PC0, PC1 and PC2) be capable of being pulled to

either the power rail or to ground based on the desired configuration. These pins can control aspects of PHYbehavior that a customer may want to change without having to create a new board or write new software. Itis recommended that for all cases but pin 2 this be done by having the following option resistors: a 1K pullupto the power rail and a 220 Ohm pulldown to ground. To program a pin either one or the other of the resistorscan be populated to set the desired functionality. Since the 220 Ohm pull-down will dominate, even if bothare installed the signal will be pulled down. Pins 2, 32 and 33 (DS2/LKON, DS1 and DS0) also controlaspects of PHY behavior that can be changed without having to create a new board or write new software,however, they are set appropriately for this reference design. See the datasheet for more information on thefunction and appropriate setting for these pins. Can also be an output, therefore it should not have a valuelower than 1K Ohm to either rail. Therefore pin 2 should have a pullup and pulldown of 1Kohm and one orthe other is populated, depending on the value to be programmed to the pin.

9)The PCLK signal is a 98.304 MHz clock signal. To reduce standing waves it is recommended a small series

resistor be included close to the PHY pin 5. The value used on the reference board is 22 Ohms.

10)Cable Not Active (CNA pin 79) output pin is just brought out to the test header pin on the reference design.

It may be left unconnected on the reference design. However it goes logic high when ever either bias (if1394a connection is made), tone, or a trained connection is made to any of the device 1394 ports. This signalmay be used by HW circuitry external to the PHY to indicate when a connection has been made to the PHY.Note that the PHY can be programmed to generate an interrupt to the link layer for the same circumstances,if SW control is desired.1)

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Figure8-2—Example FW800 design (ports 1 and 2)

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Figure 8-2 Continued

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Notes on figure8-2.

This reference design is for a PC add-in card, where the system has a chassis ground for ESD and EMI control.

2)3)

This design uses 1394b bi-lingual connectors. These connectors are used when the PHY port may be either a 1394a port or a 1394b port. What mode the port talks is determined by what type of device is plugged into the port from the other side of the connection. It is recommended that customers use the surface mount connectors with through-hole mounting pegs that are soldered into the board for more rigid connections.The outside shield of the connector should be tied to chassis ground to provide a low impedance path to thechassis ground for ESD currents.

Pin 6 is the VG ground return for cable power and speed signal current. Pin 9 is the ground return for TPB(the transmitting pair of a 1394b port). Both of these pins should be via-ed to the board ground plane as soonas possible. Pin 5 is the ground return for TPA (the receiving pair of a 1394b port), it is isolated from localground for future definition in the standards. See 1394b paragraph 5.5.1.

Connector pins 5, 6, 8, and 9 each have an ESD capacitor connecting them to chassis ground. This is in anattempt to dump as much ESD energy as possible to chassis ground before it gets distributed onto the localboard ground plane. Therefore these capacitors should be placed as close as possible to the connector andbefore the pins are via-ed to the board ground plane. This must be traded off for better ground connection(make traces fat).

The ferrite bead on the VP pin (pin 8) of the connector is placed for both ESD and EMI reasons. The 0.001uF capacitor on the PHY side of the ferrite is meant to provide a low impedance path to local ground for anyhigh frequency EMI currents that might exist on the VP power trace. The 0.001uF capacitor on the 1394bconnector side of the ferrite is meant to provide a low impedance path to chassis ground for fast rise timeESD currents that might have coupled onto the VP trace from the cable. The ferrite is meant to present a highimpedance to both of these currents, forming a “PI” filter.

The transmission line termination networks are required and should be placed close to the PHY as possible(see layout recommendations). The 1uF capacitor is to provide charge for 1394a speed signaling. The 270pfcapacitors at the mid-points of both the TPA and TPB pairs termination network is to provide common modefiltering for noise reduction and EMI reduction.

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Figure8-3—Example FW800 design (port 3 and PHY power)

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Notes on figure8-3.

The regulator provides power to the low voltage core circuitry of the PHY. The ferrite bead is meant to provide noise fil-tering to prevent noise generated from the digital circuitry from contaminating the PLL circuitry. The regulator chosenprovides 200mA and is a low noise regulator.

8.1Layout recommendations for S800 1394b TSB81BA3 Physical Layer:

In order of prioritya)

Twisted Pair Transmission Lines

1)The twisted pair lines must be very clean. The bit rate is 1Gbps (raw with out coding loss), this implies very

tight tolerances for jitter and edge placement. The minimum rise time for 1394b is 80ps. An 80ps rise time gives a critical etch length of 4.7mm. What this is saying is that the twisted pair lines MUST be laid out as controlled impedance (110 Ohm differential) transmission lines. The layout for the twisted pair transmission lines should be as short as possible. An individual twisted pair should have less than 10 mils difference between the lengths of the lines. The lines need to come together and be run as a pair until they connect to the PHY terminals.

2)The termination network must have a minimal effect on the transmission lines. For the reference layout, “fly-by” termination was used. This means the transmission lines were run directly from the connector to the PHYwithout disruption. Then the termination resistor network was placed on the back side of the board to allowthe signals to “fly-by” the PHY terminals before being terminated. This also reduces the stub length from thetermination resistors to the end of the transmission line.

3)To ensure that there is a good ground return path from the PHY terminals to the connector, at a minimum it

is recommended that a solid ground plane, without cuts, be implemented. This plane should extendimmediately below the PHY, the PHY twisted pair terminals, the twisted pair transmission lines and theterminals of the 1394b connector to the point that the connector ground return terminals (pins XX) are via-edto this solid ground plane. Via the connector ground return pins and the power gnd connector pin to the solidgnd plane as quickly as possible.

4)It is required that at least a 4 layer PWB be used to ensure the good ground return path for the 500MHz

signaling.Oscillator

1)The oscillator must be laid out to minimize noise introduced into the PHY PLL circuitry. The oscillator must

be located as close as physically possible to the PHY XI input terminal. A wide low impedance etch should be used to connect the oscillator to the PHY XI terminal. This connection should be short and direct. The TSB81BA3 requires an input voltage of 1.8V. The selected oscillator outputs 3.3V. This requires a voltage shift to the lower levels required by the PHY. The means selected in the reference design was a resistor divider. Note that this also must be done with care. The location of the resistors was done to minimize the disruption to the 98.304MHz transmission line from oscillator to PHY terminals.

2)The oscillator was laid out with a mini-power plane just for the oscillator. This power plane was isolated by

a filter from the other power planes both to reduce the noise to the oscillator, but also to reduce the noiseintroduced from the oscillator to the rest of the board. This plane also helped minimize the impedance fromthe decoupling capacitors to the power inputs of the oscillatorPower Plane Decoupling

1)PLL power plane decoupling - tbd2)Analog Power plane decoupling - tbd3)Digital power plane decoupling - tbdPHY Link interface

1)There are two 98.304MHz clocks on the PHY link interface. These traces need to be spaced well away from

the other PHY-link interface pins to reduce coupling onto the other lines and those lines acting as antennas to radiate the noise to other part of the board. There are source terminating resistors close to the source of each of these clocks. Making room for the resistors pushed the other traces away. The other traces were routed with more than minimum spacing to comfortably route from PHY to link.

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The switching power supply was placed well away from the other active circuitry on the board. This is toisolate the switching noise away from active and especially analog circuitry.Thermal Land underneath PHY

It is strongly recommended, though not required, that a thermal land be placed underneath the PHY.

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Figure8-4—PCI Connector Reference

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9.9.1Circuit Protection Needs for Firewire Devices – Introduction

At various places in this guide, there are recommendations for adding circuit protection when implementing FireWire(IEEE 1394) ports on electronic devices to ensure the robustness of the application while in field service. Two major areasare considered: power circuits and signal circuits. This section provides additional information on circuit protection,including a discussion of events that can cause circuit damage, industry standards on circuit protection, placement of pro-tection devices in a circuit, and typical device types that are used.

In order to ensure high yields in the manufacturing process, basic EOS (Electrical Overstress) protection features areimplemented within a 1394 PHY (physical layer device). However, it should be noted that they are optimized for themanufacturing environment and designed for those respective test standards (HBM, MM, and CDM). Application-leveltesting to ensure EMC compliance uses a different model that includes more severe current surges at higher voltages. Theon-chip protection devices often cannot protect against these events and supplemental protection can be added at theboard level to ensure reliable performance of the application. In general, for robust port design, all pins of a 1394 portshould be protected as described herein. This includes ESD, EOS and overcurrent protection.

In Figure 1, a notebook computer that implements a number of interface ports is shown. Specifically, it includes 1394ports. The occurrence of user-originated electrical threats should be expected as these ports are used by the consumer toconnect the notebook to various peripherals (printer, external storage, digital camcorder, etc.). During connect and dis-connect actions, incidents such as ESD, Late VG or fault current may occur.

Electrostatic Discharge (ESD) occurs when electrical charge is transferred from one object to another. In this case, theuser or the cable can become electrically charged, and then discharged through the 1394 port. Late VG occurs when theground connection is lost, but the power bus is active in the cable. Power is forced onto the data pairs and damages thePHY. Fault current can occur because of a faulty cable or connector (bent pin, etc.) or due to a metal object temporarilyinserted into the connector. Details on the electrical threats as well as potential solutions will be provided in the follow-ing sections of this document.

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Figure9-1—Overview of notebook computer showing implementation of IEEE 1394 ports.

9.2“Hot” Connection Problems (also known as “Late-VG”)9.2.1Background

All 1394 PHY devices are susceptible to electrical overstress damage when exposed to a combination of high voltagecable power and a faulty cable or connector system that allows data (TPx) and cable power (Vp) connections to engagebefore the cable ground (Vg) connection. This set of circumstances is known as a “Late Vg” event. This document pro-vides information on how to recognize a 1394 PHY device that has been damaged by a Late Vg event, an explanation ofhow the damage occurs and suggestions on both decreasing the frequency of Late Vg events in a system and protecting1394 PHY devices from damage due to Late Vg events.54

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The IEEE 1394A-2000 specification calls for 1394 cable power (Vp) to range from 8 VDC up to 30VDC with a maxi-mum current of 1.5A. Legacy IEEE 1394-1995 systems can support cable power of 8 VDC up to 40VDC, also with amaximum of 1.5A current. A typical 1394 PHY device has an absolute maximum input voltage rating of -0.5 VDC toVdd + 0.5 VDC, where the maximum value of Vdd is 4.0 VDC. There is an obvious potential for catastrophic damage toa 1394 PHY device if the voltage levels of Vp are expressed on the differential pair signals of the 1394 PHY device.If the Vp connection and any of the data (TPx) connections of two 1394 nodes are engaged before the Vg connection dueto extreme angling of the cable during connection or if the Vg connection is not well connected due to distressed cablesor connectors, some of the voltage on Vp of the 1394 cable can appear on TPx signals. For example, referring to Figure2, it can be seen how pins 1 and 3 can be connected before or without the pin 2, Vg, connection.

The Vp voltage appears on the TPx signal(s) because the data connection is used as a ground return path in lieu of the Vgconnection. The high voltage and current on the return ground path can damage the TPx inputs of the 1394 PHY deviceson both sides of the cable. ESD protection circuitry implemented inside the 1394 PHY device cannot protect against aLate Vg event because it is of longer duration and higher current than a typical ESD event. It should be noted that onlyone of the TPx connections is required for a Late Vg event to occur. A node with only Vp and TPB* connected wouldstill be susceptible to Late Vg damage.

Figure9-2—1394 6-pin receptacle (connector) and plug (cable) diagrams.

9.2.2Symptoms of 1394 PHY Device Damage due to a Late Vg Event

To the end user, a 1394 port damaged by a Late Vg event will simply fail to operate. In most cases, the other ports of thesame 1394 PHY device are not affected and continue to work properly. Replacing the damaged 1394 PHY will fix theissue completely since no other portion of the application is typically affected.

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When a damaged PHY device is bench tested, it is likely to show continuity failures. Most often there is an open or shorton one of the TPA lines of the failing port. Alternately, damage on the TPB pair is also seen in 1 out of 4 cases. Ancil-lary damage to the TPBIAS circuitry has been observed in some cases as well.

A full failure analysis of a 1394 PHY device that has experienced a Late Vg event will often show a failure mechanismof damage to metal, polysilicon and die substrate resulting in the short to ground or open, consistent with electrical over-stress. Excerpts from previous failure analyses of EOS damaged PHY devices are shown below. This is damage whichis indicative of a Late Vg event. Not every 1394 PHY damaged by a Late Vg event will show the exact same damagepattern.

9.2.3Characteristics of Applications Susceptible to Late Vg Events

Some 1394 applications are more susceptible than others to 1394 PHY damage due to Late Vg events. Characteristics ofthese applications are listed below for reference. Please note that these characteristics are not required for a Late Vgevent nor do they indicate that a Late Vg event will definitely occur. This list is purely informative. It is provided toallow a designer to determine if Late Vg is likely to be a concern for their application.

Cable Powered System: The damage caused by a Late Vg event is linked to cable power that is seeking a return path,thus systems that rely heavily on 1394 cable power are more likely to see Late Vg damage. A Late Vg event cannot occuron a 1394 node where only a 4 connection (TPA, TPA*, TPB, TPB*) receptacle is used. If there is no Vp connection, byextension there can be no damage. In addition, self-powered applications (a system which never sources or sinks currentfrom the 1394 cable) typically do not see Late Vg events. It is, however, theoretically possible for a 1394 self-powerednode to experience damage due to a Late Vg event, if it is a two port application that is repeating power to a 1394 devicethat is cable power consumer.

High Voltage on Vp: The IEEE 1394A-2000 specification limits Vp supported on the 1394 bus to 30VDC. Typical PCapplications source 10VDC-12VDC on Vp driven by the PCI bus. Damage to 1394 PHY devices due to a Late Vg eventoccurs most often on systems with greater than 15VDC on Vp. The increase in voltage that a PHY device is exposed toduring a Late Vg event also increases the likelihood of device damage.

1394 6-Pin Connectors: Late Vg events can occur on 1394B systems implementing 9-pin connections, however the 13946-pin connector is much more susceptible to angled cable insertion or even cable reversal due to its geometry. Thisincreases the likelihood of a Late Vg event.

Repetitive Cable Use: In the majority of cases of 1394 PHY devices with EOS damage investigated by Texas Instru-ments, the root cause has been traced back to a single cable or system in the manufacturers test process. Heavily used1394 cables or connectors can become worn or damaged after thousands of insertions, resulting in a degraded or nonexis-tent Vg connection which translates to an extremely high incidence of Late Vg events.

Hot Plug: In a 1394 system with intact 1394 cables and connectors, a Late Vg event is only possible during a cable inser-tion where Vp is already actively powered. If all 1394 nodes are cabled before cable power is applied, damage due to aLate Vg event is not possible, unless the Vg connection is somehow subsequently lost or broken.

9.2.4Explanation of a Late Vg Event

When the Vp connection and any of the four data (TPx) connections between two 1394 nodes, one a power provider andthe other a cable power consumer, are engaged without a Vg connection, the data connection becomes the lowest imped-ance ground return path to the Vp provider. The voltage and current on the ground return path can damage the TPx inputsof the 1394 PHY devices on both sides of the cable.

Figure 3 shows a schematic of possible electrical connections between a power provider node (NODE A) and a cablepower consumer (NODE B) during a late Vg event. For this explanation, it can be assumed that there is no direct groundconnection between the two 1394 nodes anywhere in the design. The cable shield in the figure is shown as shorted tochassis ground with no connection to signal ground on either 1394 node. 56

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The Vp connection can be assumed to occur first because it is a longer pin in the connector, thereby raising all signals onNODE B to the level of Vp. Once a data connection is made between the two nodes, the ground of NODE B is pulleddown and the voltage regulator on NODE B will engage. Since the data connection is acting as the ground return path,this forces the TPA/TPA* of NODE B in the figure to be pulled below the 1394 PHY device ground. This low voltage ismost likely outside of the absolute maximum input voltage rating of -0.5VDC on the 1394 PHY device and can result indamage to the 1394 PHY device on NODE B.

Figure9-3—Overview of Late Vg event occurring during cable operation.

As the voltage regulator of NODE B begins driving out, additional current will be returned through the data connectionraising the voltage on the TPB / TPB* signals of NODE A in the example. Depending on the cable power voltage of thesystem, the voltage on TPB/TPB* could be in excess of the absolute maximum input voltage rating of Vdd+0.5VDC onthe 1394 PHY device and can result in damage to the 1394 PHY device on NODE A.

Thus a Late Vg event can cause damage on either the power provider node or the power consumer node. In a real worldsituation, the Vg connection is likely to appear after a short delay or in the case of damaged cables or connectors, the con-nection could be intermittent. While this may limit the exposure of the 1394 PHY devices to the effects of acting as theground return path, it can also introduce transients that may cause additional damage to the devices.

9.2.51394 PHY Device Protection – Late Vg events

Passive Solution: It is possible to decrease the frequency of Late Vg events by addressing cable and connector quality issues, however,these events remain a concern for many 1394 applications. While there is no way to conclusively protect 1394 PHYdevices against all EOS damage that could be caused by a Late Vg event, it is possible to limit the effects.

One easy-to-implement suggestion is to provide an alternate low impedance ground return path by shorting the chassisground of the cable shields to digital (signal) ground. This can be done through a low impedance filter to prevent excessnoise if needed.

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Another option is to add high speed switching double diode circuits like the BAV99 to each of the TPx lines to protectthem from damaging voltages without affecting signal integrity. Figure 4 shows how these preventative measures can beimplemented in a typical 1394a application. Refer to Figure 5 for the details of a typical 1394b application.

When the elevated voltage is impressed on a data line, the diode will break over in the forward direction and shunt theLate Vg current to the power rail. Later, when the Late Vg condition is resolved, the diode will transition to its off stateand data signals can again move down the data pairs. It should be noted that the use of these diodes may be limited infuture, higher-speed versions of IEEE 1394 implementations. The parasitic capacitance of the diodes may cause sufficientsignal distortion that signal integrity is compromised.

Figure9-4—An example of Late Vg protection implementation using diodes in 1394a port

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Figure9-5—An example of Late Vg protection implementation using diodes in 1394b port

Active Solution: Another approach to Late Vg protection is to use active circuitry to monitor the condition of the power and signal linesand to react by disabling power during a Late Vg event. Referring to Figure 6, the current limiting IC monitors the outputof the comparator and if the ESD and Late Vg rail is at a higher bias than the 3.3V rail, power will be disabled. The inputto the ESD and Late Vg are the BAV99 diodes that break over during the Late Vg event.

Note that this solution can also be used to provide overcurrent protection during fault events. The sense resistors (refer-enced below in Note 1) are used to set the trip current, and essentially provide a “programmable” feature as the trip levelvaries as a function of resistance value. In the below example, 0.02? resistors set the trip level at 2.4A. As the resistancevalue is increased, the trip level decreases.

Lastly, more information can be found by reviewing the Maxim data sheet as well as their Application Note (AN3984)which discusses the use of the MAX5944 (dual port) and MAX5943 (single port) solutions.

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Figure9-6—An example of Late Vg protection implementation using a Maxim protection IC.

9.3VP Line Fault Currents

When a FireWire device is powered by the system power bus, the VP line from the 1394 port to the PHY should be pro-tected from fault currents on the bus. Fault currents occur when a component connected to the power bus fails or is dam-aged such that its resistance value dramatically drops. Likewise, power-providing FireWire devices should be protectedagainst user misapplications or defective connections (bent or broken cable/pins, etc.). To protect the PHY from highpass-through (fault) currents, this Guide recognizes the use of resettable fuses, because they have the ability to reset(restore power) after a fault current event is cleared/removed.

Resettable fuses can prevent damage from excessive currents, and then restore the circuit to normal operation when thatlevel of current is no longer present. Typically, these devices are positive temperature coefficient (PTC) thermistors,whose resistance increases due to self-heating (I2R), and thereby limit current in the line on which they are installed.Their use is recommended in FireWire equipment because of its hot-plug IEEE1394 ports, which can be exposed tounpredictable or frequent fault current events on the VBUS line.

Various PTC manufacturer ratings are available, from 6VDC to 72VDC, and 100mA to 9A. Surface mount and radial leadform factors can be supplied. In keeping with FireWire power specifications, resettable fuses should be rated for at least33VDC operation. See Figure 7 which demonstrates the use of this device. When the fault current event is cleared andcurrent drops to a normal level, the PTC cools and its resistance also goes back to normal, restoring proper operation ofthe circuit. This removes the need for warranty claim that would occur if a single-shot fuse was used.

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9.4Electrostatic Discharge (ESD)9.4.1Origins

Damage to the FireWire port from electrostatic discharge (ESD) is generally caused by the transfer of static electricalcharge from the human body to an electronic circuit. The accumulation of this charge on a body is due to frictional (tri-boelectric) forces, and can amount to tens of thousands of volts. It is also possible for ESD to transfer high peak voltagesand currents into electronic circuits due to inductive and capacitive mechanisms in cables and ungrounded devices. Anexample of this phenomenon is “Cable Discharge Event” or CDE.

9.4.2Component Sensitivity to ESD

As IC manufacturers continue to scale down device dimensions, the transistors, interconnections, and silicon layersbecome more susceptible to breakdown or electrical overstress damage due to ESD. Although IC manufacturers typicallyadd some form of ESD protection to their products, this is intended to protect them during wafer fabrication and back-endassembly processes. Lately, the trend has been to reduce the level of on-chip protection in the interest of gaining higherdevice speeds, saving wafer space, and enhancing production processes. Therefore, user-induced ESD far surpasses thevulnerability threshold of standard semiconductor devices, and may cause any of the following effects:

Soft Failures – ESD currents can change the state of internal logic, causing data corruption, erratic operation, orsystem latch-up, which may require rebooting.

Latent Defects – The system may function properly for a while until the damaged component and system eventuallyfail (prematurely).

Catastrophic Failures – The current produced by severe ESD transients can melt silicon and semiconductor inter-connects. It can also cause semiconductor junction failures due to insulating oxide breakdown. Regardless of failuremechanism, the components and the system are permanently inoperable.

ESD is characterized by very fast rise times and high peak voltages, so the protective devices within the PHY must havea similarly fast response time and voltage withstand rating. In those cases where the PHY is vulnerable to ESD, addi-tional ESD protection devices are needed at the board level. Typically, the IEC 61000-4-2 test specification is used toverify the reliability of the system against ESD. It should be noted that this specification does not require that ESD tran-sients be pulsed into open (unconnected) ports. This configuration is common in applications either during setup or ifthey are portable like Notebook computers. Passing the IEC specific my grant a false sense of security and it is recom-mended that after EMC testing is complete, ESD testing should be redone such that ESD is pulsed into open connectors.

9.4.3ESD Standards

Since ESD is the most common cause of semiconductor device failures, several industry standards and specifications havebeen developed to test and qualify integrated circuits to determine their ESD sensitivity. These include:a)b)c)

Human Body Model (HBM) in MIL-STD-883, Method 3015Machine Model (MM) in EIAJ IC121

Charged Device Model (CDM) in US ESD DS 5.3

All three of these models relate primarily to the manufacture and testing of an IC, but can also be applied to circuits andassemblies. The differences relate to the electrical models (charge capacitor and discharge resistor) that are used to sim-ulate the respective transients. Details are shown below in Figure 9-7 and Table 1.

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Figure9-7—Generalized test circuit for protection devices and end products.

Table9-1—Test circuit variables for Figure 9-7

One of the most severe standards is IEC 61000-4-2 from the International Electrotechnical Commission and referenced inthe EMC directive. This test specification applies to the completed system (computer, printer, etc.), as opposed to the inte-grated circuit as in the standards identified above. Level 4 of this test method is the highest level, subjecting the deviceunder test to the 8kV contact discharge method (preferred), and/or a 15kV air discharge.

The designer should be aware of the ESD ratings of the semiconductors used in FireWire circuits. For example, a semi-conductor device rated by a manufacturer to 2kV per MIL-STD-883 may not actually survive when subjected to the moresevere IEC test method. Additionally, even if semiconductors meet some level of ESD immunity according to IEC stan-dards, this does not imply that additional ESD suppression is not required. As mentioned earlier, real world ESD tran-sients can exceed the peak currents and voltages as defined by the standards and can have much faster rise times. Also, aparticular level of immunity may be prescribed for electromagnetic compatibility of an end product.

In a 1394 interface, protection devices should be implemented in parallel to the high-speed TPx lines to shunt ESD awayfrom sensitive PHY input circuitry. Therefore, in addition to the appropriate level of voltage immunity, an ESD suppres-sor must have low capacitance to prevent the loading and distortion of data signals.

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9.4.4Protection Criteria

Generally, ESD is the greatest threat to TPx lines, having fast rise times to peak values up to tens of thousands of volts.Protection devices must limit those peaks to much lower values, and quickly clamp residual voltages to even lower levelsas current is drained to ground. Furthermore, the capacitance value of an ESD suppressor must be low enough to notcause signal distortion on the TPx lines.

9.4.5Suppressor Characteristics

Several different technologies exist for ESD suppression on TPx lines. Given the need for low parasitic capacitance, thereare generally two technologies to consider: silicon protection arrays (SPAs), and polymeric suppressors. These technolo-gies have their own unique characteristics that should be considered during ESD protection selection. Silicon ProtectionArrays have the lowest turn-on and clamping voltages, so should be considered for PHYs that are particularly sensitive toESD. Polymeric suppressors have the lowest capacitance values, so should be considered where the capacitance budgetis being used up and it is necessary to minimize parasitic capacitance.

9.4.6Representative Circuits and Products

Depending on circuit design and cost constraints, a single channel ESD suppressor might be used for each of the fourTPX lines, as depicted in the lower circuit in Figure 8. Another option is to use a multichannel silicon protection array forthe data lines as shown in the upper circuit in Figure 8.

Figure9-8—Various options for fault current and ESD protection for 1394 port.

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Technology

Number of Channels

Voltage Peak Clamp Rating, ESD Voltage, VDCVoltage, V

V5.524

160550

2060

Peak Current Rating, A3030

Typical Mounting Cap., StylepF0.650.06

SMDSMD

SPA1Polymeric Device2

Table9-2—Representative products for ESD protection of TPx lines.

Footnotes:

1) Littelfuse SP3003-04ATG Silicon Protection Array or equivalent.2) Littelfuse PGB1010603 PulseGuard® suppressor or equivalent.3) All devices tested in accordance with IEC 61000-4-2.

9.4.7Consideration of Parasitic Capacitance Effects

Parasitic capacitance effects on signal integrity will depend on the version of 1394 that a FireWire device is designed for,and the specific data rate through that device (100MHz, 200MHz, 400MHz, etc.). As capacitance of the ESD suppressorand data rate of the port increase, the amount of distortion to leading and trailing edges of the signal pulses increases.Eventually, distortion is sufficient to interfere with data transmission.

A digital oscilloscope can be used to observe the signal with and without ESD protection on the TPx lines. Figure 8 illus-trates the effects of parasitic capacitance at 100MHz and 500MHz for three different ESD suppressor technologies and asurface mount capacitor for comparison. Low capacitance devices have virtually no effect on the test signal. Its greencurve is essentially superimposed on the yellow (no ESD suppressor) curve.

In order to confirm that the ESD suppressor capacitance level is appropriate, it is recommended that signal integrity test-ing (eye diagram, time domain reflectometry, etc.) is performed prior to the design being considered final..

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Figure9-9—Effects of parasitic capacitance on signal integrity at 100 and 500 MHz.

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10.Note, this section needs to be updated.

CPA sense

PHYpower out

V Reg

cable power

source

configurable current limit1.5A current

limit

VP0

battery/trickle

power

1.5A current

limit

VP1

cable not current current power sleeplimit limit onsenseconfig

VP VP

controlextendVP0 VP1 sensesense

Figure10-1—Example extendible two port power management IC

The power manager IC operates when power is applied to one or more of Cable Power Source, Battery/Trickle PowerSource, VP0, VP1 and VPextend.

VP0 and VP1 switches must be able to pass current in either direction, and should operate for voltages in the range 7V -33V.

VP control should be such that if no input is applied to it, then the switches are closed (pass current). (Suggest internalpull-down to VG)

Regulator should provide up to 1W at 3.3V to PHY Power Out if more than 7V is provided on any of the power sources.The configurable current limit (for supply protection) should be configurable to operate between 0.5A and 3A (resistor orI2C control). The current limit sense output shall be active if the current limit has tripped.

The 1.5A current limits should respond to overload in <10ms. The VP0 and VP1 sense pins are active if the correspond-ing current limit has tripped.

The CPA sense output should be a simple “or” of cable power of the two ports. This signal should be conditioned to beacceptable to common PHYs.

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Forward loss through diodes should be less than 0.7V... better if switches with polarity detect is used instead to minimizeforward loss (otherwise the part will consume too much power).

NOTE—For 3 or more ports, two devices can be used and ganged together by connecting their VP control and VP extend pins(allowing the switched voltage to be forwarded from any VP to any other VP).

CPA sensePHY power V out

Regcable power sourceVP0battery/trickle power

VP1VGVP0 VP1 sensesenseVP control

VP extend busPHY power out (unused)V RegVP0VP1VGVP0 VP1 sensesenseFigure10-2—Using multiple two port power management ICs

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11.[1] IEEE Std 1212-2001, Standard for a Control and Status Registers (CSR) Architecture for microcomputer buses[2] IEEE Std 1394-1995, Standard for a High Performance Serial Bus

[3] IEEE Std 1394a-2000, Standard for a High Performance Serial Bus—Amendment 1[4] IEEE Std 1394b-2002, Standard for a High Performance Serial Bus—Amendment 2[5] 1394 TA 1999001-1, Power Specification, Part 1: Cable Power Distribution, October 5, 1999[6] 1394 TA 1999001-3, Power Specification Part 3: Power Distribution Management, January 15, 2000

This standard shall also be used in conjunction with the following publications under development. When approved as astandard, the approved version shall apply.

[7] NCITS TR-25-1999 1-SEP-1999 Information Technology - Fibre Channel - Methodologies for Jitter Specification - MJS1[8] NCITS T11/02-127v2 3-AUG-2002 Information Technology - Fibre Channel - Methodologies for Jitter and Signal QualitySpecification - MJSQ

[9] 1394 Open Host Controller Interface Specification, Release 1.1, January 6, 2000[10] 1394 Open Host Controller Interface Specification, Release 1.2.

[11] TI Application Note SLLA117, IEEE 1394 EMI Board Design and Layout Guidelines, Jose A. Cadena-Hernandez, BurkeHenehan, Lee Myers, Revision 1.1.3, July 2002

[12] TI Application Note SLLA020A, Recommendations for PHY Layout, Ron Raybarman, March 1999

[13] LSI Application Note AP00041-02, FW323/FW322 Hardware Implementation Design Guideline. Revision 2, December2002

NCITS T11.2 working documents are available at http://www.t11.org.

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12.These definitions a liberally borrowed from the 1394b specification.

12.1Conformance terminology

Several keywords are used to differentiate between different levels of requirements and optionally, as follows:

12.1.1expected: A keyword used to describe the behavior of the hardware or software in the design models assumed by thisstandard. Other hardware and software design models may also be implemented.

12.1.2ignored: A keyword that describes bits, bytes, quadlets, octlets or fields whose values are not checked by the recipient.12.1.3may: A keyword that indicates flexibility of choice with no implied preference.

12.1.4reserved: A keyword used to describe objects—bits, bytes, quadlets, octlets and fields—or the code values assigned tothese objects in cases where either the object or the code value is set aside for future standardization. Usage and interpretationmay be specified by future extensions to this or other standards. A reserved object shall be zeroed or, upon development of afuture standard, set to a value specified by such a standard. The recipient of a reserved object shall not check its value. Therecipient of a defined object shall check its value and reject reserved code values.

12.1.5shall: A keyword indicating a mandatory requirement. Designers are required to implement all such mandatoryrequirements to ensure interoperability with other products conforming to this standard.

12.1.6should: A keyword indicating flexibility of choice with a strongly preferred alternative. Equivalent to the phrase “isrecommended.”

12.2Technical glossary

The following are terms that are used within this standard:

12.2.18B/10B: A line code that maps 8 bit symbols to 10 bit symbols so as to achieve DC balance and bounded disparity.12.2.2acknowledge: An acknowledge packet.

12.2.3acknowledge packet: An 8-bit packet that may be transmitted in response to the receipt of a primary packet. The mostand least significant nibbles are the one's complement of each other.

12.2.4acronym: A contrived reduction of nomenclature yielding mnemonics (ACRONYM).

12.2.5active port: A connected, enabled port that is capable of detecting all Serial Bus signal states and participating in thereset, tree identify, self-identify and normal arbitration phases.

12.2.6arbitration: The process by which nodes compete for control of the bus. Upon completion of arbitration, the winningnode is able to transmit a packet or initiate a short bus reset.

12.2.7asynchronous packet: A primary packet transmitted in accordance with asynchronous arbitration rules (outside of theisochronous period).

12.2.8attached peer PHY: A peer cable PHY at the other end of a particular physical connection from the local PHY.12.2.9B cloud: A collection of B nodes and/or Border nodes in which all inter-node connections are made through Beta ports.

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12.2.10B link: A link which is capable of operating according to the specifications given in clause 14 or 15 of 1394b, and inparticular issues requests appropriate to BOSS arbitration.

12.2.11B bus: An operating bus in which all nodes are operating as B PHY’s.12.2.12B node. A node whose PHY is operating as a B PHY.

12.2.13B only PHY: A PHY which is only capable of B PHY mode of operation, i.e. all its ports are Beta-only ports and itslink, if any, is a B link or a PIL.

12.2.14B-parallel link: A mode of Link operation in which the PHY-Link signalling is provided to the PHY using a parallelinterface.

12.2.15B PHY: A mode of PHY operation in which all the logically connected ports are operating in Beta mode and the link,if any, is not configured to operate in Legacy PHY-link mode.

12.2.16base rate: A data rate of 98.304Mbits/s ± 100 ppm. In a cable environment, all Legacy capable nodes are capable ofcommunicating at this rate and all B capable nodes are capable of communicating at 4 * base rate.

12.2.17BER: Bit error ratio. The ratio of the number of bits received in error to the total number of bits received.

12.2.18Beta Mode: When a port is operating according to the specifications given in clauses 10, 11, and 13 of 1394b and, inparticular, is using the 8B/10B symbol coding and obeying the BOSS arbitration protocols then the port is in Beta Mode. Thespeed of a port sending in Beta Mode is denoted by the β suffix (e.g., S400β)12.2.19Beta port: A port that is operating in Beta Mode.

12.2.20Beta-only port: A port that is only capable of operating as a Beta port.

12.2.21bilingual port: A port that is capable of operating both as a Beta port and as a DS port. One of the modes is selectedat the time that the logical connection is made; which one is selected depends on the capabilities of the peer port.12.2.22Border node: A node with both

(i) either its link operating as a B link or at least one Beta port or both, and (ii) either its link operating as a Legacy link or at least one DS port or both.

12.2.23BOSS: An acronym for Bus Owner/Supervisor/Selector. In a B cloud, the BOSS is the node currently responsible fortaking arbitration decisions. A node becomes BOSS by virtue of being the last node to transmit data in a subaction (in general,this is the node transmitting an acknowledge to a non-broadcast asynchronous packet, or the primary packet transmitter in allother cases), or by receiving a grant. The BOSS determines the end of the fairness interval and the end of isochronous inter-vals, notifying the other nodes. Finally, the BOSS selects the path to grant next, thereby passing the BOSS rights and responsi-bilities to another node.

12.2.24BOSS arbitration: The arbitration scheme defined by this standard. The principle features of BOSS arbitration arethat the node making the arbitration decision varies (see BOSS), and that arbitration requests may be overlapped with datatransmission and both isochronous and asynchronous requests may be pipelined for the succeeding isochronous interval orfairness interval respectively.

12.2.25bus ID: A 10-bit number uniquely specifying a particular bus within a system of multiple interconnected buses.12.2.26byte: Eight bits of data.

12.2.27cable PHY: Abbreviation for the cable physical layer.

12.2.28cable physical layer: The version of the physical layer applicable to the Serial Bus cable environment.

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12.2.29CAT-5: Category 5 UTP cable.

12.2.30character: A 10-bit sequence of data sent on a connection that is operating in B mode.12.2.31concatenated transaction: A split transaction comprised of concatenated subactions.

12.2.32connected PHY: A peer cable PHY at the other end of a particular physical connection from the local PHY.12.2.33connection: Two ports that can communicate with each other and the media between those two ports.

12.2.34connection tone: Signal used to indicate that a port is capable of operating in Beta mode. Also confirms that a con-nection exists between two Beta-mode capable ports.

12.2.35CSR Architecture: ISO/IEC 13213:1994 [ANSI/IEEE Std 1212, 1994 Edition], Information technology-Micropro-cessor systems-Control and Status Registers (CSR) Architecture for microcomputer buses.12.2.36cycle master: The node that generates the periodic cycle start packet 8000 times a second.12.2.37cycle start: Synonymous with cycle start packet.

12.2.38cycle start packet: A primary packet sent by the cycle master that indicates the start of an isochronous interval.12.2.39data bit: The smallest signaling element used by the physical layer for transmission of packet data on the medium.12.2.40data character: A character used by the 8B/10B code.

12.2.41Data Strobe (DS): A signaling method using two signals in which one signal (Data) always indicates the binary valueof the data (0 or 1) and the other signal (Strobe) changes if the data stays the same during successive bit cells. This signalingmethod is used in IEEE Std 1394-1995 and IEEE Std 1394a-2000.

12.2.42DC balance: The requirement that over long runs of binary symbols there be no net disparity.

12.2.43destination: A node that is addressed by a packet. If the destination is individually addressed by a source, then it hasto return an acknowledge packet.

12.2.44disabled port: A port configured to neither transmit, receive or repeat Serial Bus signals. A disabled port shall bereported as disconnected in a PHY's self-ID packet(s).

12.2.45disconnected port: A port whose connection detect circuitry detects no peer PHY at the other end of a cable.12.2.46disparity: The number of ones in a transmission character minus the number of zeros in a character.12.2.47doublet: Two bytes, or 16 bits of data.

12.2.48DS mode: The form of electrical signaling and handshaking that is compatible with IEEE Std 1394-1995 and IEEEStd 1394a-2000.

12.2.49DS only port: A port only capable of operating as a DS port.

12.2.50DS port: A port that is operating according to Legacy specifications, in particular using DS electrical signaling andobeying the arbitration protocols defined therein. A DS only port or a bilingual port can operate as a DS port.12.2.51EIA: Electronic Industries Association.

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12.2.52eye diagram: Oscilloscope display of the physical layer signal which is triggered on a bit edge and shows many dif-ferent bit patterns overlaid on top of each other.

12.2.53fairness interval: A time period delimited by arbitration reset indicators. Within a fairness interval, the total numberof asynchronous packets that may be transmitted by a node is limited. Each node's limit may be explicitly established by thebus manager or it may be implicit.

12.2.54FOP: A fanout PHY. A multi-ported PHY that is attached to a PIL using the serial interface defined in clause 15 of1394b.

12.2.55galvanic isolation: A mechanism to avoid low frequency ground loop currents.12.2.56gap: A period of idle bus.

12.2.57Hybrid bus: An operating bus that contains at least one Border node.12.2.58IEC: International Electrotechnical Commission.

12.2.59initial node space: The 256 terabytes of Serial Bus address space that is available to each node. Addresses within ini-tial node space are 48 bits and are based at zero. The initial node space includes initial memory space, private space, initial reg-ister space and initial units space. See either ISO/IEC 13213:1994 or IEEE Std 1394-1995 for more information on addressspaces.

12.2.60initial register space: A 2048 byte portion of initial node space with a base address of FFFF F00016. This addressspace is reserved for resources accessible immediately after a bus reset. Core registers defined by ISO/IEC 13213:1994 arelocated within initial register space as are Serial Bus-dependent registers defined by IEEE Std 1394-1995.

12.2.61initial units space: A portion of initial node space with a base address of FFFF F000 80016 This places initial unitsspace adjacent to and above initial register space. The CSR's and other facilities defined by unit architectures are expected tolie within this space.

12.2.62ISO: International Organization for Standardization.

12.2.63isochronous: Uniform in time (i.e., having equal duration) and recurring at regular intervals.

12.2.isochronous gap: On a Legacy bus, the period of idle bus following an isochronous subaction that precedes asynchro-nous arbitration.

12.2.65isochronous interval: A period that begins after a cycle start packet is sent and ends with a subaction indication. Dur-ing an isochronous interval, only isochronous subactions may occur. An isochronous interval begins, on average, every 125 μs.12.2.66isochronous resource manager: A node that implements the BUS_MANAGER_ID, BANDWIDTH_AVAILABLE,CHANNELS_AVAILABLE and BROADCAST_CHANNEL registers (some of which permit the cooperative allocation ofisochronous resources). Subsequent to each bus reset, one isochronous resource manager is selected from all nodes capable ofthis function.

12.2.67isochronous subaction: Within the isochronous interval, either a concatenated packet or a packet and the gap thatpreceded it.

12.2.68isolated node: A node without active ports; the node's ports may be disabled, disconnected or suspended in any com-bination.

12.2.69jitter: Any variation in the zero-crossing time from the ideal bit pattern.

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12.2.70Legacy: Characteristics or behavior of a link, node, PHY, cable or connector defined by IEEE Std 1394-1995 or IEEEStd 1394a-2000.

12.2.71Legacy cloud: A collection of Legacy nodes and/or Border nodes in which all inter-node connections are madethrough Legacy ports.

12.2.72link: Abbreviation for the link layer. Also, the physical entity that implements the link layer. Also, one of the compo-nents connected to the PHY-link interface.

12.2.73link layer: The Serial Bus protocol layer that provides confirmed and unconfirmed transmission or reception of pri-mary packets.

12.2.74logically connected port: A port whose “connected” status is TRUE. If a port is physically connected to a peer whichis not powered then the port is not logically connected.

12.2.75low-power connection signaling: Signaling, based on the exchange of very low duty cycle tones, by which the con-nectivity status of a port is determined. This takes place when the port is not active or is disabled.12.2.76module: The smallest component of physical management; i.e., a replaceable device.

12.2.77Near-End Cross-Talk (NEXT): The noise induced in the receiving pair due to the signal on the transmitting pair onthe same port. For example, the signal on the TpB pair can cause NEXT on the TpA pair of a port.

12.2.78node: A Serial Bus device that may be addressed independently of other nodes. A minimal node consists of only aPHY without an enabled link. If the link and other layers are present and enabled they are considered part of the node. 12.2.79node controller: A component within a node that provides a coordination point for management functions exclu-sively local to a given node and involving the application, transaction, link and physical elements located at that node.12.2.80node ID: A 16-bit number that uniquely differentiates a node from all other nodes within a group of interconnectedbuses. The 10 most significant bits of node ID are the same for all nodes on the same bus; this is the bus ID. The six least-sig-nificant bits of node ID are unique for each node on the same bus; this is called the physical ID. The physical ID is assigned asa consequence of bus initialization.

12.2.81non-return to zero: (NRZ): A signaling technique in which a polarity level high represents a logical 1 (one) and apolarity level low represents a logical level 0 (zero).

12.2.82null packet: A packet in which no data is transmitted.12.2.83octlet: Eight bytes, or bits, of data.

12.2.84operating speed: Nominal speed at which a port operating in Beta mode is communicating clocked information withits peer, measured in Mbits/s (before 8B/10B encoding), usually identified with the “S” notation (e.g. S100, S200, S400, etc.).12.2.85originating port: A transmitting port on a PHY which has no active receiving port. The source of the transmittedpacket is either the PHY's local link or the PHY itself.

12.2.86packet: a sequence of zero or more bits transmitted on Serial Bus and delimited by packet start symbol and a packetend symbol.

12.2.87packet speed: The data rate of a packet (necessarily less than or equal to the operating speed of a Beta-mode connec-tion used to transmit the packet).

12.2.88path: The concatenation of all the physical connections between the link layers of two nodes.

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12.2.payload: The portion of a primary packet that contains data defined by an application.12.2.90PCB: Printed circuit board.

12.2.91peer: Service layer on a remote node at the same level. For instance a peer link layer is the link layer on a differentnode.

12.2.92PIL: PHY integrated with Link. A link that uses a modified Beta port to attach to a fanout PHY using the protocolsdefined in clause 15.

12.2.93PHY packet: A -bit packet where the most significant 32 bits are the one's complement of the least significant 32bits.

12.2.94physical connection: The full-duplex physical layer association between directly connected nodes. In the case of thecable physical layer, this is a pair of physical connections running in opposite directions.

12.2.95physical ID: The least-significant six bits of the node ID. On a particular bus, each node's physical ID is unique. 12.2.96physical layer (PHY): The Serial Bus protocol layer that translates the logical symbols used by the link layer intoelectrical signals on Serial Bus media. The physical layer is self-initializing. Physical layer arbitration guarantees that only onenode at a time is sending data. The mechanical interface is defined as part of the physical layer. There are different physicallayers for the backplane and for the cable environment.

12.2.97physical link: In the cable physical layer, the simplex path from the transmit function of the port of one node to thereceive function of a port of a directly connected node.

12.2.98ping: A term used to describe the transmission of a PHY packet to a particular node in order to time the responsepacket(s) provoked.

12.2.99PLL: Phase Locked Loop.

12.2.100PMD: Physical Medium Dependent.

12.2.101PMD interface: The part of an interface that is specific to single kind of interconnect.

12.2.102Point-to-point (P2P) Packet: Special packet type that is sent on the PIL-FOP interface. This packet is used to carrydata that cannot be sent as part of a normal Serial Bus packets.

12.2.103port: The part of the PHY that allows connection to one other node.

12.2.104primary packet: Any packet that is not an acknowledge or a PHY packet. A primary packet is an integral number ofquadlets and contains a transaction code in the first quadlet.

12.2.105primary power provider: A node that provides at least 20V and declares it’s power sourcing capabilities in its self-ID packet. Other restrictions and requirements are included in the TA Cable Power Distribution document.12.2.106quadlet: Four bytes, or 32 bits, of data.

12.2.107random jitter: Jitter that comes from random sources. Characterized by gaussian statistics and unbounded variationaccording to the gaussian distribution function.

12.2.108receiver eye opening: The interval in time within a bit period where the sampled data value will have a probabilityof error less than the specified bit error ratio (BER).

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12.2.109register: A term used to describe addresses that may be read or written by Serial Bus transactions. In the context ofthis standard, the use of the term register does not imply a specific hardware implementation. For example, in the case of splittransactions that permit sufficient time between the request and response subactions, the behavior of the register may be emu-lated by a processor within the module.

12.2.110repeating port: A transmitting port on a PHY that is repeating a packet from the PHY's receiving port. 12.2.111request: A primary packet (with optional data) sent by one node's link (the requester) to another node's link (theresponder).

12.2.112response: A primary packet (with optional data) sent in response to a request subaction.12.2.113restore: The process of causing a connection in standby to return to the active state.12.2.114resume signal: A signal requiring the port to resume normal operations.

12.2.115resuming port: A previously suspended port which has observed signaling other than the connection tone or hasbeen instructed to resume. In either case, the resuming port engages in a protocol with its connected peer PHY in order to rees-tablish normal operations and become active.

12.2.116run length: The length of a sequence of bits that have the same value, e.g., 1's or 0's.

12.2.117running disparity: An estimate of the running digital sum at the end of a character sub-block, based upon the mostrecently transmitted (or received) character sub-block. When initialized with the same value, the running disparity and runningdigital sum will be equal at the end of any character sub-block. Errors in a received character stream may result in the runningdisparity being not equal to the running digital sum.

12.2.118scrambler: Transmitted signals are chosen from the set of all possible symbols by using both the desired symbol anda pseudo-randomly generated offset pointer. Used to average out the spectral content of the transmitted signal to avoid strongspectral lines.

12.2.119senior border: A unique border node in a B cloud. The senior border is the last node to originate a self-ID packetwithout a speed code into the cloud (i.e. repeated from a DS-mode port or generated because of a Legacy link), and is respon-sible for ensuring that certain Legacy gap timings are observed.

12.2.120self-ID packet: A PHY packet transmitted by a cable PHY during the self-ID phase or in response to a PHY pingpacket.

12.2.121Serial Bus management: The set of protocols, services and operating procedures that monitors and controls the var-ious Serial Bus layers - physical, link and transaction.12.2.122source: A node that initiates a bus transfer.

12.2.123split transaction: A transaction where unrelated subactions may take place on the bus between its request andresponse subactions.

12.2.124STP: Shielded, twisted pair.

12.2.125standby: A low-power state of a Beta connection in which only low-power connection signaling takes place. No busreset is generated as a result of a port entering or leaving the standby state.

12.2.126standby initiator: An active port that transmits the STANDBY configuration request and engages in a protocol withits connected peer PHY to place the connection into the standby state.

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12.2.127subaction: A complete link layer operation minimally consisting of a packet transmission. The packet may beoptionally preceded with bus arbitration and optionally followed by an acknowledgment.

12.2.128subaction gap: In a Legacy cloud, period of idle bus that precedes arbitration for an asynchronous subaction.12.2.129suspend: To go into a low-power mode of operation while maintaining low-power connection signaling. When aport enters or leaves the suspend state a bus reset is generated.

12.2.130suspend initiator: An active port that transmits the SUSPEND configuration request or the TX_SUSPEND signaland engages in a protocol with its connected peer PHY to place the connection in the suspend state.

12.2.131suspend target: An active port that receives the SUSPEND configuration request or observes the RX_SUSPENDsignal. A suspend target requests that all of the other active ports on the PHY become suspend initiators while the suspend tar-get port engages in a protocol with its connected peer PHY to suspend the connection.12.2.132suspended node: An isolated node with at least one port that is suspended.

12.2.133suspended port: A connected port not operational for normal Serial Bus arbitration but otherwise capable of detect-ing either a physical cable disconnection or a resume signal.

12.2.134synchronization: The process of aligning the receiver's circuits to properly detect received bits and to properlydetect symbol boundaries.

12.2.135TDR: Time Domain Reflectometry.

12.2.136TIA: Telecommunications Industry Association.

12.2.137transaction: A request and the optional, corresponding response.

12.2.138transaction layer: The Serial Bus protocol layer that defines a request-response protocol for read, write and lockoperations.

12.2.139unit: A component of a Serial Bus node that provides processing, memory, I/O or some other functionality. Once thenode is initialized, the unit provides a CSR interface. A node may have multiple units, which normally operate independentlyof each other.

12.2.140unit architecture: The specification document that describes the interface to and the behaviors of a unit imple-mented within a node.

12.2.141unit interval: The nominal amount of time 1 bit takes to transmit.12.2.142UTP: Unshielded Twisted Pair.

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