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专利名称：TEST APPARATUS AND REPAIR ANALYSIS
METHOD
发明人：Kenichi FUJISAKI申请号：US13298207申请日：20111116
公开号：US20120120748A1公开日：20120517
专利附图：
摘要：A test apparatus that tests a memory under test, comprising an address failmemory that stores address fail data for each address; a block fail memory that storesblock fail data for each block; a reading section that reads the address fail data from the
address fail memory for each block; a row fail counter that, for each row address in agroup including a plurality of the blocks in the memory under test, counts the fail cellsindicated by the address fail data; and a column fail counter that counts the fails cells foreach column address.
申请人：Kenichi FUJISAKI
地址：Saitama JP
国籍：JP
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