PON-MAC芯片BL2000介绍

PON MAC芯⽚（DS-BL2000）介绍1、主要接⼝1.1数字接⼝

●Dual Fast Ethernet 10/100 (IEEE 802.3/802.3u)●Gigabit Ethernet 10/100/1000 (IEEE 802.3ab/802.3z)●Native TDM GEM Interface

●Peripheral Bus Interface (PBI) for glueless interface to common industry1.2光接⼝

Integrated 2488/1244Mbps CDR

Glueless interface to BPON and GPON Multi-Source Agreement (MSA) Small FormFactor (SFF) transceivers1.3 TDM接⼝TDM Interface

Native TDM over GEM via an companion FPGA2、以太⽹MAC2.1配置以太⽹接⼝

●Fast Ethernet 10/100 (IEEE 802.3/802.3u)MII or dual RMII MAC InterfaceHalf and full duplex support

●Gigabit Ethernet 10/100/1000 (IEEE 802.3ab/802.3z)GMII MAC Interface

●Configurable 802.3x hardware flow control●IEEE 802.1q VLAN tagging2.2、GPON MAC

●The GPON MAC supports Ethernet packet and TDM payload transport over the PONinterface through GPON Encapsulation Mode (GEM). It supports ITU-T G.984.x set ofstandards with extended functionalities●Compliant to G.984.x●Multiple data rates

●Configurable AES encryption on DS payload●Configurable FEC on US and DS payload

●Dedicated connections for In-band management can be directed to CPU2.3、BPON MAC

BroadLight’s ITU-T G.983 MAC is industry proven and FSAN interoperable.●G.983.1 compliant

●G.983.2 (OMCI) compliant●G.983.4 (DBA) compliant●Multiple data rates●Queue manager●32 VP/VC group filters

●ATM cell processing with end-to-end OAM per I.610●Derives clock from recovered network clock2.4、CDR, SerDes

●PCML TX and LVPECL RX interface levels●Variable Data rates

●Selectable reference clock frequency 78 MHz or 155 MHz

●Integrated on-chip 50Ω termination resistor in the transmitter and in the receiver3、Cell/Packet Processor

信源、包处理引蟼是为了优化GPON或者BPON数据平台流处理器。信源、包处理引蟼包括：AAL5-SAR，AAL2-SAR，802.1d-bridge学习，ATM整形和策略。包含核⼼处理和硬件加速器，在时钟频率为200MHz可达到300K packets/s。3.1固件

●Supports up to 100 Mbps full duplex sustained Ethernet traffic with -byte packets●Support for 512 filtering table entries●Support for 802.1p, 802.1q and 802.1D

●ATM cell processing and Ethernet packet processing using AAL5 adaptation method●Support of RFC-2684 with VC multiplexing or LLC encapsulation3.2硬件

●32-bit instructions and register data width●Thirty two general purpose registers●16 KB instruction address space●48 KB memory data space

●256 addresses for I/O data space (used by HW accelerators)●Several data addressing modes●32-bit ALU and 32-bit shift unit●Byte mask operations

●32-bit accumulator register used as output for each part of the execution unit●Special instructions for activating HW accelerators and networking purposes such asscheduling4、核⼼处理单元

The BL2000’s embedded CPU is a general purpose MIPS32 based controller that provides control plane functionality for theONT system and for PON operation。

5、MIPS⼦系统●32-bit 4KEc RISC core●16 KB I-Cache, 8 KB D-Cache●Memory Management Unit (MMU)

●Single-stepping of the processor as well as instruction and data virtual address beakpointsvia EJTAG

6、系统接⼝单元（SIU）

6.1 Programmable General Purpose I/O (GPIO)●21 Bidirectional General Purpose I/O● 3.3 V tolerant inputs●TTL/Open collector outputs●4mA current to drive LEDs6.2 Peripheral Bus Interface (PBI)

●24-bit address bus clocked up to 66 MHz

●Configurable bus clock (BUSCLK): rates of 20 MHz, 25 MHz, 33 MHz, 50 MHz, and 66MHz

●Configurable wait states of up to 20 BUSCLK cycles●Peripheral byte access support

●Support for asynchronous and synchronous bus accesses

●Configurable assertion, de-assertion, and polarity for CS, RW, and TS6.3 Interrupt Controller

●Servicing up to 6 edge or level external sources and 21 internal sources.●Different interrupt priority levels

●Programmable priority level and mask per interrupt source6.4 UART●32-Byte buffers

●Selectable baud rate from 9600 Bytes–115.2 KBytes6.5 I2C

●Master transmitter and receiver●32-Byte buffers

●Support of inter-bit and inter-byte clock stretching6.6 Serial Peripheral Interface (SPI)●Limited to control plane applications●Operation in master mode

●Full duplex master transmit/receive

6.7 Timers

●Configurable SW watchdog timer●Three general purpose 32-bit timers6.8 Power Management

●Sleep mode (Outgoing Calls Only)●Low Power Mode (Lifeline)6.9 External Memory●200 MHz DDR2 SDRAM●16-bit data bus6.10 JTAG

●IEEE 1149.1 compliant, JTAG boundary scan7、物理层说明1.V oltages●Core 1.2V ±5%

●I/O 2.5V ±0.2V (3.3V tolerant)●DDR 1.8V ±0.1V

2.27 x 27mm 1mm pitch Pb-free BGA Package

3.Absolute maximum power dissipation 1.9 W, typical 1 W

4.Operating temperature -40°C to 85°C without forced air cooling 8、数据结构8.1 结构框图

8.2 任务消息

信源、包处理任务通信包含硬件接⼝间的握⼿和固件之间握⼿硬件外围固件任务内部固件任务内存管理状态机8.3 GPON MAC

●GPON MAC使得以太⽹包和TDM承载在PON接⼝，⽤GEM的封装模式●它⽀持ITU-T G.984.x标准的扩展接⼝功能

●GPON MAC是在PON和包处理器间响应GEM SAR功能，其也⽀持PON连接间上下T-CONT队列状态机的QoS功能8.3.1 RX

Supports rates of 1.244 Gbps and 2.488 Gbps

125µs frame synchronization based on physical synchronization field and on the ident field De-Scrambling according toG.984.3 definition using an X7+X6+1 polynomialBIP support in order to measure the link BER

Supports PLOAM handling: including ONU-ID filtering, receiving of broadcast PLOAMs,and CRC checkSupports Plend data length extraction and check; including CRC

Supports payload filtering according to a 32 PORT-ID mapping table. Discards payloads that do not belong to the ONU andIDLE GEM fragments.

Supports FEC decoder RS(239,255)

Supports AES decryption (counter mode only with 128 bytes of Key) of GEM payload.Configured encryption option is per ONU.

Supports GEM header removal and data extraction (GEM SAR)Supports interleaving of 32 RX flows of 32 PORT-IDs

Supports one TDM RX flow of up to 20 Mbps on the TDM Interface

Supports three discard thresholds: low, high, and very high (data, PLOAM, and OMCI) Supports packet CRCPasses relevant US BW map information to the TX unitConfigurable Enable/DisableIncludes PM counter blockIncludes Interrupt block8.3.2 TX

Supports rates of 0.622 Gbps or 1.244 GbpsEight T-CONTS

Supports one TDM TX flow at 20 Mbps from the TDM interface to one of the eight payload T-CONTSAdditional T-CONT for normal PLOAMSRX unit synchronization

Upstream frame generation based on US BW accesses (Overheads + payload)PLOu and PLSu overhead generation based on configured parametersScrambling according to G.984.3 definition using an X7+X6+1 polynomialBIP generation to measure the link BER

Static, urgent, and ranging PLOAM generated by the MIPS

Supports GEM header insertion and data segmentation (GEM SAR)Supports packet CRC calculationSupports Idle GEM frame transmission

Scheduler to control frame generation and transmission based on US BW records.Supports FEC encoder RS (239,255)Configurable Enable/Disable

Automatic disable when RX is disabled

8.3.3 下⾏流

GPON下⾏流，⼊⼝GEM帧是指定到具体包放置在适当的RX队列中。基于它们的port-id，这些包被放置在各⾃握⼿任务的以态桥队列或者CPU队列。在桥队列中先是在扩展前区分，然后分包送⼊出⼝队列。

8.3.4 上⾏流

上⾏以太⽹包基于优先级被放置在不同的发送队列中，如基于cos，tos或者桥接等，每⼀个发送队列备连接到⼀个单播流Tcont。每⼀个Tcont能维护⼀个优先级表。每⼀个Tcont都被指定⼀个唯⼀id，以太⽹包通过多port-id能够合并为独⽴的id。8.3.5 信源/包处理流程

The Cell/Packet Processor handler interfaces with the GPON TX and GPON RX peripherals and the BroadBus.BroadBus physical format adapterTX SM supports:

o Round robin filling TX queues

o The transport layer of the BraodBus to enable control and data forwarding for the TX queuesRX SM supports:

o Push data from GPON MAC RX FIFO to the Cell/Packet Processor SRAMo Manage the RX FIFO in the SRAM by BroadBus messages:

Transmit Messages: RX buffer descriptor, Cell/Packet Processor wakeup, and RX payloadReceive Message: ACK indicating RX buffer is read by the processor and the buffer is empty8.3.6 GEM Port Interface (TDM)

The GEM interface includes a TX clock, TX data, a RX clock, and RX data. The TX clock is generated by the BL2000 and is19.44 MHz, which is derived directly from the PON clock. The RX clock is generated by an external component, thecompanion TDM FPGA, and is up to 19.44 MHz.

8.3.7 GPON Activation Flow

8.4 BPON MAC

8.4.1 The BL2000 BPON MAC features include:BPON compliance standardso G.983.1

TC Layer framing and de-churningITU I.432.1 scramblingRanging

Physical Layer OAM (PLOAM)Full OAM faults and alarmo G.983.2 (OMCI)

o G.983.4 (DBA)

SR-DBA for enhanced QoS control and peak bandwidth allocationInternal or external queue status reporting on mini-slotsSupported data rates:

o Downstream: 1.244 Gbps or 622 Mbpso Upstream: 155 Mbps

Four level QoS support for upstream trafficQueue manager

o Eight Traffic Containers (T-Conts)

o Flexible assignment of queues for upstream, downstream or CPUo Flexible assignment of queue size and watermarkSupport for 32 VP/VC group filterso SFU/SBE application is assumedo 32-bit header masko Promiscuous mode

Support for up to 32 active AAL5 flows

Support for all five types of T-CONTs: types 1, 2, 3, 4 and 5A TM cell processing with end-to-end OAM per I.610Derives clock from recovered network clock

Enables 8 KHz clock generation from PLOAM SYNC bytes

Dedicated connections for In-band management can be directed to CPU (ATM OAM or OMCI)8.4.2 Downstream Flow

8.4.3 Received PLOAM Cell Structure

8.4.4 Upstream Flow

8.4.5 Upstream Cell Handler

8.4.6 Loopbacks

8.5 以太⽹MAC

For subscriber Ethernet traffic, two Media Access Control (MAC) modules are available. These allow the BL2000 to functionin either dual Fast Ethernet mode or single Gigabit Ethernet mode. In dual Fast Ethernet mode, the physical device interfaceis a dual Reduced Media Independent Interface (RMII). In single Gigabit Ethernet mode, the physical device interface is aGigabit Media Independent Interface (GMII). The Gigabit MAC is an auto-negotiating 10/100/1000 MAC and may alsooperate in Media Independent Interface (MII) mode. The Gigabit MAC also includes the MAC Control sublayer, which

provides support for Control frames including PAUSE frames.General Ethernet features include:Fast Ethernet 10/100 (IEEE 802.3/802.3u)o Four modes of operationOne MIIOne RMIIMII and RMIIDual RMII

o Half and full duplex support

Gigabit Ethernet 10/100/1000 (IEEE 802.3ab/802.3z)o GMII MAC Interface

Configurable 802.3x flow control

CPU flow control Ethernet port by host command to generate Pause frame Programmable watermarks for full/empty FIFOconditions for automatic generation of pause frames based on FIFO fill levels. Backpressure issupported for half duplex mode.

Configurable enable/disable MDIO interfaceSupport of MTU up to 2 KBytesIEEE 802.1q VLAN taggingVLAN tagging according to 802.1pq

VLAN tag to GEM Port mapping for US traffic: VID or TCIQ-in-Q (802.1q VLAN stacking/stuffing)

Provides statistic counters to support OMCI and RMON implementation9、MIPS Subsystem

The MIPS Subsystem consists of a MIPS RISC core (CPU), peripherals, and gluelogic. The Subsystem includes a 4KEcMIPS core, 16 KB 2-way Instruction cache, 8 KB 2-way Data cache, Peripheral Bus Interface, Interrupt Controller, UART,I2C, SPI, GPIO, Timers, and register access to all BL2000 units.The CPU has the following main features:

High-performance, low-power, 32-bit 4KEc RISC coreSingle clock multiply operationMemory Management Unit (MMU)I-Cache 16 KB, 2-Way Set Associative

D-Cache 8 KB, 2-Way Set Associative, supporting write-back and writethrough operations Cache line locking supportNon-blocking pre-fetches

MIPS 32 Privileged Resource Architecture

Single-stepping of the processor as well as instruction and data virtual address/value breakpoints via EJTAG

4.1. MIPS Core

The MIPS 4KEc core has the following features:Five stage pipeline

32-bit address and data pathsMIPS 32 Release 2 instruction setI-Cache 16 KB, 2-Way Set Associative

D-Cache 8 KB, 2-Way Set Associative, supporting write-back and writethroughoperations

16-byte cache line sizeNon-blocking pre-fetches

One-clock multiplier (specific to 4KEc core)Programmable Cache Sizes

o Individually configurable instruction and data cacheso Direct Mapped, 2-, 3-, or 4-Way Set Associativeo 16-byte cache line sizeo Non-blocking pre-fetches

One-clock multiplier (specific to 4KEc core)

Programmable Memory Management Unit (specific to 4KEc core) o Sixteen dual-entry Joint TLB (JTLB) with variable pagesize

o Four entry Instruction TLB (ITLB)o Four entry Data TLB (DTLB)Multiply/Divide Unit

o Maximum issue rate of one 32x16 multiply per clocko Maximum issue rate of one 32x32 multiply every other clock

o Early-in iterative divide (minimum 11 and maximum 34 clock latency) ?Power-down mode (triggered by WAIT instruction)EJTAG debug1EC Bus

o Works in sequential burst mode

o Burst can start from any address and wraps around on burst limito MIPS accesses have a constant burst size of 16 bytes (4 clock cycles)