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专利名称：CMOS integrated circuit for signal delay发明人：Norio Tomisawa申请号：US06/914377申请日：19861001公开号：US04742254A公开日：19880503
摘要：A CMOS integrated circuit for signal delay comprises CMOS gate circuitsconnected in multiple stages which deliver out an input binary signal after delaying it by apredetermined delay time. The CMOS gate circuits are arranged in a folded pattern on anintegrated circuit substrate and each row of the folded pattern including a part of theCMOS gate circuits in stages of an odd number. Each of the CMOS gate circuits consists ofan N channel element and a P channel element cascade- connected to each other andgate patterns of the respective channels have their width and length adjusted in such amanner that value of operating currents in these elements become equal to each otherwhen the same external voltage has been applied to these elements.
申请人：NIPPON GAKKI SEIZO KABUSHIKI KAISHA
代理机构：Spensley Horn Jubas & Lubitz
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